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FAN9612 Arkusz danych(PDF) 7 Page - Fairchild Semiconductor

Numer części FAN9612
Szczegółowy opis  Design Consideration for Interleaved Boundary Conduction Mode PFC
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Producent  FAIRCHILD [Fairchild Semiconductor]
Strona internetowa  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

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AN-6086
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.4 • 4/22/10
7
Figure 11. Input Voltage Sensing
The line peak detection circuit is saturated when VIN
exceeds 3.7V, as depicted in Figure 11. Therefore, line
feedforward does not work for VIN higher than 3.7V, as
illustrated in Figure 12. The minimum brownout protection
trip point that allows proper line feedforward operation for
universal line range is 66VAC (265VAC×0.925/3.7). When
the brownout protection threshold is lower than 68VAC for
universal range input, line feedforward can be lost for high
line and, therefore, the limited output power increases as
line voltage increases:
..
2
()
3.7
MAX NO FF
MAX
IN
OUT
OUT
V
PP
=⋅
(17)
Another effect of VIN sensing saturation is that the phase
management threshold as a percentage of nominal output
power increases as peak of VIN increases above 3.7V
because the line feedforward does not work above 3.7V.
Since FAN9611/12 uses peak detection for the line voltage
sensing, it is typical to use a small capacitor (CINF) to
bypass switching noise. To minimize the effect of sensing
delay, the RC time constant between RIN2 and CINF should
be smaller than 5% of AC line period.
Figure 12. VIN Feedforward Range
(Design Example) Setting the brown-out protection
threshold at 70VAC and selecting RIN1=2MΩ, RIN2 is
obtained as:
1
2
,
6
(2
/ 0.925 1)
210
18.9
2 70 / 0.925 1
IN
IN
LINE UVLO
R
R
V
k
=
×
=
⋅−
Assuming the hysteresis for brownout protection is
3VAC, RIN,HYS is obtained as:
.2
,1
12
3
6
66
3
2
()
2
2 3
18.9 10
(2 10 )
1.1
2 10
2 10
18.9 10
LINE HYS
IN
IN HYS
IN
IN
IN
VR
RR
AR
R
k
μ
=−
+
⋅×
=
−×
=
Ω
××
+
×
RIN.HYS can be omitted since the hysteresis of 2.8VAC is
obtained without RIN,HYS from Equation 15. CINF is
selected as 10nF, which results in RC time constant as:
39
2.
(
)
18.9 10 10 10
189
IN
IN HYS
INF
R
RC
s
τ
μ
=+
=
×
⋅ ×
=
[STEP-4] Determine MOT Pin Resistor
The on time of the gate drive signal is proportional to the
compensation voltage as shown in Figure 13. The
compensation voltage is internally clamped at 4.3V where
the maximum on time is obtained. The Maximum On Time
(MOT) of the gate drive signal of each channel is
programmed by the resistor on the MOT pin as:
12
2
12
,
2
230 10
(
)
2
IN
IN
ON MAX
MOT
IN
LINE
RR
tR
RV
+
=⋅
×
(18)
As can be observed in Equation 18, the maximum on time
is inversely proportional to the square of line voltage due
to the line feed-forward operation.
The MOT resistor should be determined by considering the
output power since the maximum on time limits the
maximum output power during overload condition as:
2
,,
,
2
LINE
MAX CH
MAX
OUT CH
ON MAX
V
PK
P
t
L
η
=⋅
=
(19)
where PMAX,CH is the limited maximum output power per
channel and KMAX is maximum power limiting factor,
which is a ratio between the limited maximum output
power and nominal output power.
Considering the tolerances of inductor, resistor, and
controller variation; it is typical to set the limited maximum
power as 20~30% higher than the nominal output power
(KMAX = 1.2~1.3).


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