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SM320F2812-HT Arkusz danych(PDF) 5 Page - Texas Instruments |
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SM320F2812-HT Arkusz danych(HTML) 5 Page - Texas Instruments |
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5 / 155 page  SM320F2812-HT www.ti.com SGUS062A – JUNE 2009 – REVISED APRIL 2010 List of Figures 2-1 SM320F2812 Die Layout ........................................................................................................ 15 2-2 SM320F2812 172-Pin HFG CQFP (Top View) ............................................................................... 16 3-1 Functional Block Diagram ....................................................................................................... 28 3-2 F2812 Memory Map (See Notes A. Through G.) ............................................................................ 28 3-3 External Interface Block Diagram .............................................................................................. 40 3-4 Interrupt Sources ................................................................................................................. 42 3-5 Multiplexing of Interrupts Using the PIE Block ............................................................................... 43 3-6 Clock and Reset Domains ...................................................................................................... 46 3-7 OSC and PLL Block .............................................................................................................. 48 3-8 Recommended Crystal/Clock Connection .................................................................................... 49 3-9 Watchdog Module ................................................................................................................ 50 4-1 CPU-Timers ....................................................................................................................... 52 4-2 CPU-Timer Interrupts Signals and Output Signal (See Notes A. and B.) ................................................. 53 4-3 Event Manager A Functional Block Diagram (See Note A.) ................................................................ 58 4-4 Block Diagram of the F2812 ADC Module .................................................................................... 61 4-5 ADC Pin Connections With Internal Reference (See Notes A and B) ..................................................... 62 4-6 ADC Pin Connections With External Reference ............................................................................. 63 4-7 eCAN Block Diagram and Interface Circuit ................................................................................... 66 4-8 eCAN Memory Map .............................................................................................................. 67 4-9 McBSP Module With FIFO ...................................................................................................... 70 4-10 Serial Communications Interface (SCI) Module Block Diagram ............................................................ 75 4-11 Serial Peripheral Interface Module Block Diagram (Slave Mode) .......................................................... 78 4-12 GPIO/Peripheral Pin Multiplexing .............................................................................................. 81 5-1 28x Device Nomenclature ....................................................................................................... 83 6-1 SM320F2812-HT Life Expectancy Curve ..................................................................................... 87 6-2 Typical Current Consumption Over Frequency ............................................................................... 89 6-3 Typical Power Consumption Over Frequency ................................................................................ 90 6-4 F2812 Typical Power-Up and Power-Down Sequence – Option 2 ........................................................ 91 6-5 Output Levels ..................................................................................................................... 92 6-6 Input Levels ....................................................................................................................... 92 6-7 3.3-V Test Load Circuit .......................................................................................................... 93 6-8 Clock Timing ...................................................................................................................... 96 6-9 Power-on Reset in Microcomputer Mode (XMP/MC = 0) (See Note A) ................................................... 98 6-10 Power-on Reset in Microprocessor Mode (XMP/MC = 1) ................................................................... 99 6-11 Warm Reset in Microcomputer Mode .......................................................................................... 99 6-12 Effect of Writing Into PLLCR Register ......................................................................................... 99 6-13 IDLE Entry and Exit Timing .................................................................................................... 100 6-14 STANDBY Entry and Exit Timing ............................................................................................. 102 6-15 HALT Wakeup Using XNMI ................................................................................................... 104 6-16 PWM Output Timing ............................................................................................................ 105 6-17 TDIRx Timing .................................................................................................................... 106 6-18 EVASOC Timing ................................................................................................................ 106 6-19 EVBSOC Timing ................................................................................................................ 106 6-20 External Interrupt Timing ....................................................................................................... 107 6-21 General-Purpose Output Timing .............................................................................................. 108 6-22 GPIO Input Qualifier – Example Diagram for QUALPRD = 1 ............................................................. 108 Copyright © 2009–2010, Texas Instruments Incorporated List of Figures 5 |
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