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GS1531-CBE2 Arkusz danych(PDF) 3 Page - Gennum Corporation

Numer części GS1531-CBE2
Szczegółowy opis  Multi-Rate Serializer with ClockCleaner
Download  50 Pages
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Producent  GENNUM [Gennum Corporation]
Strona internetowa  http://www.gennum.com
Logo GENNUM - Gennum Corporation

GS1531-CBE2 Arkusz danych(HTML) 3 Page - Gennum Corporation

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GS1531 Data Sheet
30573 - 7
February 2008
3 of 50
Contents
Key Features.................................................................................................................1
Applications...................................................................................................................1
Description ....................................................................................................................1
Functional Block Diagram .............................................................................................2
1. Pin Out .....................................................................................................................5
1.1 Pin Assignment ...............................................................................................5
1.2 Pin Descriptions ..............................................................................................6
2. Electrical Characteristics........................................................................................13
2.1 Absolute Maximum Ratings ..........................................................................13
2.2 DC Electrical Characteristics ........................................................................13
2.3 AC Electrical Characteristics.........................................................................14
2.4 Solder Reflow Profiles...................................................................................16
3. Input/Output Circuits ..............................................................................................17
3.1 Host Interface Maps......................................................................................19
3.1.1 Host Interface Map (Read Only Registers).........................................20
3.1.2 Host Interface Map (R/W Configurable Registers) .............................21
4. Detailed Description ...............................................................................................22
4.1 Functional Overview .....................................................................................22
4.2 Parallel Data Inputs.......................................................................................22
4.2.1 Parallel Input in SMPTE Mode............................................................23
4.2.2 Parallel Input in DVB-ASI Mode..........................................................23
4.2.3 Parallel Input in Data-Through Mode..................................................23
4.2.4 Parallel Input Clock (PCLK) ................................................................24
4.3 SMPTE Mode................................................................................................25
4.3.1 Internal Flywheel.................................................................................25
4.3.2 HVF Timing Signal Extraction.............................................................25
4.4 DVB-ASI mode..............................................................................................26
4.4.1 Control Signal Inputs ..........................................................................27
4.5 Data-Through Mode......................................................................................28
4.6 Additional Processing Functions...................................................................28
4.6.1 Input Data Blank .................................................................................28
4.6.2 Automatic Video Standard Detection..................................................28
4.6.3 Packet Generation and Insertion ........................................................30
4.7 Parallel-To-Serial Conversion .......................................................................37
4.8 Serial Digital Data PLL..................................................................................38
4.8.1 External VCO......................................................................................38
4.8.2 Lock Detect Output .............................................................................38
4.8.3 Loop Bandwidth Adjustment ...............................................................39
4.9 Serial Digital Output ......................................................................................39
4.9.1 Output Swing ......................................................................................39


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