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5V9885TNLGI Arkusz danych(PDF) 6 Page - Integrated Device Technology |
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5V9885TNLGI Arkusz danych(HTML) 6 Page - Integrated Device Technology |
6 / 39 page 6 INDUSTRIALTEMPERATURERANGE IDT5V9885T 3.3V EEPROMPROGRAMMABLECLOCKGENERATOR Spread Spectrum Pre-Divider (D) Values Multiplier (M) Values Programmable Loop Bandwidth Generation Capability PLL0 1 - 255 2 - 8190 yes yes PLL1 1 - 255 2 - 8190 yes yes PLL2 1 - 255 1 - 4095 yes no REFERENCE CLOCK INPUT PINS AND SELECTION The 5V9885T supports up to two clock inputs. One of the clock inputs (XTALIN/ REFIN) can be driven by either an external crystal or a reference clock. The second clock input (CLKIN) can only be driven from an external referenceclock.Eitherclockinputcanbesetasatheprimaryclock. Theprimary clock designation is to establish which is the main reference clock to the PLLs. Thenon-primaryclockisdesignatedasthesecondaryclockincasetheprimary clock goes absent and a backup is needed. The PRIMCLK bit (0x34) determines which clock input will be the primary clock. When PRIMCLK bit is "0",itwillselectXTALIN/REFINastheprimary,andwhen"1",itwillselectCLKIN as the primary. The two external reference clocks can be manually selected using the GIN5/CLK_SEL pin, except in Manual Frequency Control (MFC) mode 2, or via programming by hard wiring the CLK_SEL pin and toggling the PRIMCLKbit. FormoredetailsontheMFCmodes,refertotheCONFIGURING MULTI-PURPOSE I/Os section. When CLK_SEL is LOW, the primary clock isselectedandwhenHIGH,thesecondaryclockisselected. TheSMbits(0x34) must be set to "0x" for manual switchover which is detailed in SWITCHOVER MODESsection. XTAL load cap = 3.5pF + XTALCAP[7:0] * 0.125pF (Eq. 1) Crystal Input (XTALIN/REFIN) Thecrystaloscillatorsshouldbefundamentalmodequartzcrystals:overtone crystals are not suitable. Crystal frequency should be specified for parallel resonance with 50Ωmaximum equivalent series resonance. When the XTALIN/REFIN pin is driven by a crystal, it is important to set the internal oscillator inverter drive strength and internal tuning/load capacitor values correctly to achieve the best clock performance. These values are programmable through either I2C or JTAG interface to allow for maximum compatibilitywithcrystalsfromvariousmanufacturers,processes,performances, and qualities. The internal load capacitors are true parallel-plate capacitors for ultra-linear performance. Parallel-plate capacitors were chosen to reduce the frequencyshiftthatoccurswhennon-linearloadcapacitanceinteractswithload, bias, supply, and temperature changes. External non-linear crystal load capacitors should not be used for applications that are sensitive to absolute frequencyrequirements.Thevalueoftheinternalloadcapacitorsaredetermined byXTALCAP[7:0]bits,(0x07).Theloadcapacitancecanbesetwitharesolution of 0.125 pF for a total crystal load range of 3.5pF to 35.5pF. This value should be set to two times the crystal load capacitance value stated by the vendor, subtracting out board capacitance value. Check with the vendor's crystal load capacitancespecificationfortheexactsettingtotunetheinternalloadcapacitor. The following equation governs how the total internal load capacitance is set. Ex.: For crystal capacitance = 12pF For board capacitance = 3pF each leg XTALCAP = 2x [12-3] = 18pF GIN5/CLK_SEL Selected Clock Input L Primary H Secondary Parameter Bits Step Min Max Units XTALCAP 8 0.125 0 32 pF When using an external reference clock instead of a crystal on the XTAL/ REFINpin,theinputloadcapacitorsmaybecompletelybypassed.Thisallows for the input frequency to be up to 200MHz. When using an external reference clock,theXTALOUTpinmustbeleftfloating,XTALCAPmustbeprogrammed to the default value of "0", and crystal drive strength bit, XDRV (0x06), must be set to the default value of "11". CLKIN Pin CLKIN pin is a regular clock input pin, and can be driven up to 400MHz. PRE-SCALER, FEEDBACK-DIVIDER, AND POST-DIVIDER Each PLL incorporates an 8-bit pre-scaler and a 12-bit feedback divider whichallowstheusertogeneratethreeuniquenon-integer-relatedfrequencies. For output banks OUT2-OUT6, each bank has a 10-bit post-divider. The following equation governs how the frequency on output banks OUT2-6 is calculated. FOUT = FIN * D (Eq. 2) Where FIN is the reference frequency, M is the total feedback-divider value, Disthepre-scalervalue,Pisthetotalpost-dividervalue,andFOUTistheresulting output bank frequency. The value 2 in the denominator is due to the divide- by-2 on each of the output banks OUT2-6. Note that OUT1 does not have any typeofpost-divider. Also,programminganyofthedividersmaycauseglitches on the outputs. Pre-Scaler D[7:0] are the bits used to program the pre-scaler for each PLL, D0 for PLL0, D1 for PLL1, and D2 for PLL2. The pre-scalers divide down the referenceclockwithintegervaluesrangingfrom1to255. Tomaintainlowjitter, thedivideddownclockmustbehigherthan400KHz;itisbesttousethesmallest D divider value possible. If D is set to '0x00', then this will power down the PLL and all the outputs associated with that PLL. M P * 2 ( ) |
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