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74FCT388915T15PYG Arkusz danych(PDF) 6 Page - Integrated Device Technology

Numer części 74FCT388915T15PYG
Szczegółowy opis  3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)
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Producent  IDT [Integrated Device Technology]
Strona internetowa  http://www.idt.com
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IDT74FCT388915T
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE)
GENERAL AC SPECIFICATION NOTES (continued):
8. The tPD spec describes how the phase offset between the SYNC input and the output connected to the FEEDBACK input, varies with process, temperature and voltage. The
phase measurements were made at 1.5V. The Q/2 output was terminated at the FEEDBACK input with 100
Ω to VCC and 100Ω to ground. tPD measurements were made with
the loop filter connection shown in Figure 1 below:
Analog loop filter section
of the FC T388915T
ANALO G VCC
ANALOG GND
LF
BO ARD G ND
BO AR D VCC
0.1
μF (Loop
Filter Cap)
0.1
μF
High
Freq.
Bypass
10
μF
Low
Freq.
Bypass
A separate Analog power supply is not necessary
and should not be used. Following these pre-
scribed guidelines is all that is necessary to use
the FCT388915T in a normal digital environm ent.
LF
External Loop
Filter
0.1
μF
C1
Analog G ND
Figure 2. Recommended Loop Filter and Analog Isolation Scheme for the FCT388915T
NOTES:
1. Figure 2 shows a loop filter and analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure stable and jitter-free
operation:
a. All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of long traces can cause undesirable
voltage transients at the LF pin.
b. The 10µF low frequency bypass capacitor and the 0.1µF high frequency bypass capacitor form a wide bandwidth filter that will minimize the 388915T's sensitivity to voltage
transients from the system digital VCC supply and ground planes.
If good bypass techniques are used on a board design near components which may cause digital VCC and ground noise, VCC step deviations should not occur at the 388915T's
digital VCC supply. The purpose of the bypass filtering scheme shown in figure 2 is to give the 388915T additional protection from the power supply and ground plane transients
that can occur in a high frequency, high speed digital system.
c. The loop filter capacitor (0.1µF) can be a ceramic chip capacitor, the same as a standard bypass capacitor.
2. In addition to the bypass capacitors used in the analog filter of Figure 2 there should be a 0.1µF bypass capacitor between each of the other (digital) four VCC pins and the board
ground plane. This will reduce output switching noise caused by the 388915T outputs, in addition to reducing potential for noise in the "analog" section of the chip. These bypass
capacitors should also be tied as close to the 388915T package as possible.
Figure 1


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