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74LV4053DB Arkusz danych(PDF) 11 Page - NXP Semiconductors |
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74LV4053DB Arkusz danych(HTML) 11 Page - NXP Semiconductors |
11 / 26 page 74LV4053_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 10 August 2009 11 of 26 NXP Semiconductors 74LV4053 Triple single-pole double-throw analog switch 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 15. Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max tpd propagation delay nYn, nZ to nZ, nYn; see Figure 13 [2] VCC = 1.2 V - 25 - - - ns VCC = 2.0 V - 9 17 - 20 ns VCC = 2.7 V - 6 13 - 15 ns VCC = 3.0 V to 3.6 V [3] - 5 10 - 12 ns VCC = 4.5 V - 4 9 - 10 ns VCC = 6.0 V - 3 7 - 8 ns ten enable time E to nYn, nZ; see Figure 14 [2] VCC = 1.2 V - 100 - - - ns VCC = 2.0 V - 34 65 - 77 ns VCC = 2.7 V - 25 48 - 56 ns VCC = 3.0 V to 3.6 V; CL =15pF [3] -16 - - - ns VCC = 3.0 V to 3.6 V [3] - 19 38 - 45 ns VCC = 4.5 V - 17 32 - 38 ns VCC = 6.0 V - 13 25 - 29 ns Sn to nYn, nZ; see Figure 14 [2] VCC = 1.2 V - 125 - - - ns VCC = 2.0 V - 43 82 - 97 ns VCC = 2.7 V - 31 60 - 71 ns VCC = 3.0 V to 3.6 V; CL =15pF [3] -20 - - - ns VCC = 3.0 V to 3.6 V [3] - 24 48 - 57 ns VCC = 4.5 V - 21 41 - 48 ns VCC = 6.0 V - 16 31 - 37 ns |
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