ADF4360-9BCPZRL7 datasheet(7/24 Pages) AD

Numer części	ADF4360-9BCPZRL7

Szczegółowy opis	Clock Generator PLL with Integrated VCO

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Data Sheet

ADF4360-9

Rev. B | Page 7 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

1

CPGND

2

AVDD

3

AGND

4

RFOUTA

5

RFOUTB

6

VVCO

15 DGND

16 REFIN

17 CLK

18 DATA

14 CN

13 RSET

TOP VIEW

(Not to Scale)

ADF4360-9

NOTE

THE EXPOSED PADDLE MUST BE CONNECTED TO AGND.

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

CPGND

Charge Pump Ground. This is the ground return path for the charge pump.

2

AVDD

Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane

should be placed as close as possible to this pin. AVDD must have the same value as DVDD.

3, 8, 11, 22

AGND

Analog Ground. This is the ground return path of the prescaler and VCO.

4

RFOUTA

VCO Output. The output level is programmable from 0 dBm to −9 dBm. See the Output Matching section for a

description of the various output stages.

5

RFOUTB

VCO Complementary Output. The output level is programmable from 0 dBm to −9 dBm. See the Output

Matching section for a description of the various output stages.

6

VVCO

Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane

should be placed as close as possible to this pin. VVCO must have the same value as AVDD.

7

VTUNE

Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP

output voltage.

9

L1

An external inductor to AGND should be connected to this pin to set the ADF4360-9 output frequency. L1 and

L2 need to be the same value. A 470 Ω resistor should be added in parallel to AGND.

10

L2

An external inductor to AGND should be connected to this pin to set the ADF4360-9 output frequency. L1 and

L2 need to be the same value. A 470 Ω resistor should be added in parallel to AGND.

12

CC

Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.

13

RSET

Connecting a resistor between this pin and CPGND sets the maximum charge pump output current for the

synthesizer. The nominal voltage potential at the RSET pin is 0.6 V. The relationship between ICP and RSET is

ICPmax = 11.75/RSET

For example, RSET = 4.7 kΩ and ICPmax = 2.5 mA.

14

CN

Internal Compensation Node. This pin must be decoupled to VVCO with a 10 μF capacitor.

15

DGND

Digital Ground.

16

REFIN

Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of

100 kΩ (see Figure 16). This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.

17

CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the

24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.

18

DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a

high impedance CMOS input.

19

LE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the

four latches, and the relevant latch is selected using the control bits.

20

DIVOUT

This output allows the user to select VCO frequency divided by A or VCO frequency divided by 2A.

Alternatively, the scaled RF, or the scaled reference frequency, can be accessed externally through this output.

21

DVDD

Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane should

be placed as close as possible to this pin. DVDD must have the same value as AVDD.

23

LD

Lock Detect. The output on this pin is logic high to indicate that the part is in lock. Logic low indicates loss of lock.

24

CP

Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn drives the

internal VCO.

EP

Exposed Pad. The exposed pad must be connected to AGND.

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Analog Devices	ADF4360-9BCPZRL7	533Kb / 24P	Clock Generator PLL with Integrated VCO

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