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AM1802 Arkusz danych(PDF) 1 Page - Texas Instruments

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Numer części AM1802
Szczegółowy opis  AM1802 ARM Microprocessor
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Producent  TI1 [Texas Instruments]
Strona internetowa  http://www.ti.com
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AM1802 Arkusz danych(HTML) 1 Page - Texas Instruments

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AM1802
www.ti.com
SPRS710C – NOVEMBER 2010 – REVISED MARCH 2012
AM1802 ARM Microprocessor
Check for Samples: AM1802
1
Device Summary
1.1
Features
12
NOR (8-/16-Bit-Wide Data)
• Highlights
NAND (8-/16-Bit-Wide Data)
– 300-MHz ARM926EJ-S™ RISC Core
16-Bit SDRAM With 128 MB Address
– ARM9 Memory Architecture
Space
– Enhanced Direct-Memory-Access Controller
– DDR2/Mobile DDR Memory Controller
3 (EDMA3)
16-Bit DDR2 SDRAM With 512 MB
– Two External Memory Interfaces
Address Space or
– Three Configurable 16550 type UART
16-Bit mDDR SDRAM With 256 MB
Modules
Address Space
– Two Serial Peripheral Interfaces (SPI)
• Three Configurable 16550 type UART Modules:
– Multimedia Card (MMC)/Secure Digital (SD)
– With Modem Control Signals
Card Interface with Secure Data I/O (SDIO)
– 16-byte FIFO
– One Master/Slave Inter-Integrated Circuit
– 16x or 13x Oversampling Option
– USB 2.0 OTG Port With Integrated PHY
• Two Serial Peripheral Interfaces (SPI) Each
– One Multichannel Audio Serial Port
With Multiple Chip-Selects
– 10/100 Mb/s Ethernet MAC (EMAC)
• One Multimedia Card (MMC)/Secure Digital (SD)
– Three 64-Bit General-Purpose Timers
Card Interface with Secure Data I/O (SDIO)
– One 64-bit General-Purpose/Watchdog Timer
Interfaces
• One Master/Slave Inter-Integrated Circuit (I2C
Bus™)
• 300-MHz ARM926EJ-S RISC MPU
• USB 2.0 OTG Port With Integrated PHY (USB0)
• ARM926EJ-S Core
– USB 2.0 High-/Full-Speed Client
– 32-Bit and 16-Bit (Thumb®) Instructions
– USB 2.0 High-/Full-/Low-Speed Host
– Single Cycle MAC
– End Point 0 (Control)
– ARM® Jazelle® Technology
– End Points 1,2,3,4 (Control, Bulk, Interrupt or
– EmbeddedICE-RT™ for Real-Time Debug
ISOC) Rx and Tx
• ARM9 Memory Architecture
• One Multichannel Audio Serial Port:
– 16K-Byte Instruction Cache
– Transmit/Receive Clocks
– 16K-Byte Data Cache
– Two Clock Zones and 16 Serial Data Pins
– 8K-Byte RAM (Vector Table)
– Supports TDM, I2S, and Similar Formats
– 64K-Byte ROM
– DIT-Capable
• Enhanced Direct-Memory-Access Controller 3
– FIFO buffers for Transmit and Receive
(EDMA3):
• 10/100 Mb/s Ethernet MAC (EMAC):
– 2 Channel Controllers
– IEEE 802.3 Compliant
– 3 Transfer Controllers
– MII Media Independent Interface
– 64 Independent DMA Channels
– RMII Reduced Media Independent Interface
– 16 Quick DMA Channels
– Management Data I/O (MDIO) Module
– Programmable Transfer Burst Size
• Real-Time Clock With 32-kHz Oscillator and
• 128K-Byte On-chip Memory
Separate Power Rail
• 1.8V or 3.3V LVCMOS IOs (except for USB and
• Three 64-Bit General-Purpose Timers (Each
DDR2 interfaces)
Configurable as Two 32-Bit Timers)
• Two External Memory Interfaces:
• One 64-Bit General-Purpose/Watchdog Timer
(Configurable as Two 32-Bit General-Purpose
– EMIFA
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to
Copyright © 2010–2012, Texas Instruments Incorporated
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.


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