TL16PNP200A

STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER

SLLS274A– APRIL1997 – REVISED MAY 1997

10

POST OFFICE BOX 655303

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

V

High level output voltage

IOH = – 4 mA (see Note 10)

VCC – 0.8

V

VOH

High-level output voltage

IOH = – 12 mA (see Note 11)

VCC – 0.8

V

V

Low level output voltage

IOL = 4 mA (see Note 10)

0.5

V

VOL

Low-level output voltage

IOL = 12 mA (see Note 11)

0.5

V

Il

Input current

VCC = 5.25 V,

VSS = 0,

±1

µA

Il

Input current

CC

,

VI = 0 to 5.25 V,

SS

,

All other pins floating

±1

µA

High impedance state output

VCC = 5.25 V,

VSS = 0,

IOZ

High-impedance-state output

current

VCC 5.25 V,

VSS 0,

VO = 0 to 5.25 V,

±10

µA

OZ

current

O

Pullup transistors and pulldown transistors are off

µ

ICC

Supply current

VCC = 5.25 V,

All inputs toggle

TA = 25°C,

25

mA

ICC

Supply current

All inputs toggle

No load on outputs

A

,

f = 22 MHz,

25

mA

Ci(CLK)

Clock input capacitance

5

pF

fCLK

Clock frequency

10

22

MHz

† All typical values are at VCC = 5 V and TA = 25°C.

NOTES: 10. These parameters apply for all outputs except D7 – D0, IRQ and CDRQ outputs.

11. These parameters only apply for D7 – D0, IRQ , and CDRQ outputs.

serial EEPROM clock timing requirements over recommended ranges of supply voltage and

operating free-air temperature

PARAMETER

ALTERNATE

SYMBOL

TEST CONDITIONS

MIN

MAX

UNIT

tw(SCLKH)

Pulse duration, SCLK high to low (see Note 12)

tCHCL

250

ns

tw(SCLKL)

Pulse duration, SCLK low to high (see Note 12)

tCLCH

See Figure 9

250

ns

fCLK

SCLK clock frequency (see Note 13)

0.3

0.68

MHz

td1

Delay time, CS high to SCLK high

tSHCH

See Figure 9

50

ns

td2

Delay time, SIO input valid to SCLK high

tDVCH

100

ns

tpd1

Propagation delay time, SCLK high to input level

transition

tCHDX

See Figures 9 and 10

100

ns

tpd2

Propagation delay time, SCLK high to output valid

tCHQV

500

ns

tpd3

Propagation delay time, SCLK low to CS transition

tCLSL

See Figure 10

2

clock

period

td3

Delay time, CS low to output Hi-Z

tSLQZ

100

ns

NOTES: 12. The ST93C56 chip select, S, must be brought low for a minimum of 250 ns (tSLSH) between consecutive instruction cycles per the

ST93C56 specification.

13. The SCLK signal is attained by dividing the internal CLK signal frequency by 32.