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SN74ACT2440 Arkusz danych(PDF) 10 Page - Texas Instruments

Numer części SN74ACT2440
Szczegółowy opis  NuBusE INTERFACE CONTROLLER
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Strona internetowa  http://www.ti.com
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SN74ACT2440 Arkusz danych(HTML) 10 Page - Texas Instruments

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SN74ACT2440
NuBus
™ INTERFACE CONTROLLER
SCHS010 – D3158, OCTOBER 1988 – REVISED JANUARY 1991
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
10
Table 2. Master Block-Transfer Function Table
A5
A4
A3
A2
A1
A0
LOCTM1
LOCTM0
BLOCK
SIZE
TYPE OF
CYCLE
X
X
X
L
H
L
L
H
2
Write
X
XL
H
H
L
L
H
4
Write
X
LH
H
H
L
L
H
8
Write
L
HH
HH
L
L
H
16
Write
X
X
X
L
H
L
H
H
2
Read
X
XL
H
H
L
H
H
4
Read
X
LH
H
H
L
H
H
8
Read
L
H
H
H
H
L
H
H
16
Read
slave block-transfer cycles
The ’ACT2440 can support slave block-transfer cycles with the addition of the ’ALS2442. The first responsibility
of a slave during block transfers is to determine the type and size of the block transfer. This information is
provided by the requesting master and must be decoded from the TMx lines and the A5–A0 address lines (as
provided by the ’ACT2420s). See Table 3 for additional details.
The slave interim acknowledge input (SIACK) generates the interim acknowledge cycles via TM0. The slave
external request output (SEREQ) signals the local board when an interim acknowledge has occurred on the bus.
Figure 14 shows the timing diagram of a typical slave block read. Figure 15 shows the timing diagram of a typical
slave block write. The beginning of these cycles looks like any other slave cycle; SEREQ goes active (low),
signaling the local board that another master is requesting the local board. On the first sample edge after SGNTA
is taken active (low), the AEN buffer signal is driven low, enabling the NuBus
™ addresses onto the local board.
The A0, A1, and TMx lines must be decoded as provided on the ’ALS2442 in order to generate a block-transfer
signal (represented on the timing diagrams as BLOCK). When this signal goes active (high), it signals the local
board that a block transfer has been requested. Decoding A5-A2 determines the number of words to be
transferred. The final acknowledge cycle is generated by driving LACK low.
Table 3. Slave Block-Transfer Decode Table
A5
A4
A3
A2
A1
A0
NTM1
NTM0
BLOCK
SIZE
TYPE OF
CYCLE
X
X
X
L
H
L
H
L
2
Write
X
XL
H
H
L
H
L
4
Write
X
LH
H
H
L
H
L
8
Write
L
HH
HH
L
H
L
16
Write
X
X
X
L
H
L
L
L
2
Read
X
XL
H
H
L
L
L
4
Read
X
LH
H
H
L
L
L
8
Read
L
H
H
H
H
L
L
L
16
Read


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