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TPA3100D2IRGZRQ1 Arkusz danych(PDF) 6 Page - Texas Instruments |
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TPA3100D2IRGZRQ1 Arkusz danych(HTML) 6 Page - Texas Instruments |
6 / 37 page 32 5 27 10 25 12 PVCCR RINP PGNDR AGND PVCCR Exposed ThermalPad RINN NC NC NC NC PGNDR LINP VCLAMPR LINN VCLAMPL NC PGNDL GAIN0 PGNDL GAIN1 PVCCL MSTR/SLV PVCCL SYNC 33 4 28 9 26 11 34 3 29 8 35 2 30 7 36 1 31 6 44 17 38 23 43 18 37 24 45 16 39 22 46 15 40 21 47 14 41 20 48 13 42 19 TPA3100D2-Q1 SLOS557 – SEPTEMBER 2008 ......................................................................................................................................................................................... www.ti.com 48 PIN, QFN PACKAGE (TOP VIEW) TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. AGND 4, 17 Analog ground for digital/analog cells in core. AVCC 48 High-voltage analog power supply. Not internally connected to PVCCR or PVCCL. BSLN 23 I/O Bootstrap I/O for left channel, negative high-side FET BSLP 18 I/O Bootstrap I/O for left channel, positive high-side FET BSRN 38 I/O Bootstrap I/O for right channel, negative high-side FET BSRP 43 I/O Bootstrap I/O for right channel, positive high-side FET TTL-compatible output. HIGH = short-circuit fault. LOW = no fault. Only reports short-circuit FAULT 46 O faults. Thermal faults are not reported on this terminal. GAIN0 8 I Gain select least significant bit. TTL logic levels with compliance to VREG. GAIN1 9 I Gain select most significant bit. TTL logic levels with compliance to VREG. GND Ground. Connect to the thermal pad. LINN 6 I Negative audio input for left channel. Biased at VREG/2 LINP 5 I Positive audio input for left channel. Biased at VREG/2 LOUTN 21, 22 O Class-D 1/2-H-bridge negative output for left channel LOUTP 19, 20 O Class-D 1/2-H-bridge positive output for left channel Master/slave select for determining direction of SYNC terminal. High = master mode, SYNC MSTR/SLV 10 I terminal is an output; low = slave mode, SYNC terminal accepts a clock input. TTL logic levels with compliance to VREG. Mute signal for quick disable/enable of outputs (high = outputs high-Z, low = outputs MUTE 45 I enabled). TTL logic levels with compliance to AVCC. 1, 7, 12, 13, NC 24, 25, 36, No internal connection 37, 47 PGNDL 28, 29 Power ground for left channel H-bridge PGNDR 32, 33 Power ground for right channel H-bridge PVCCL 26, 27 Power supply for left channel H-bridge, not internally connected to PVCCR or AVCC. PVCCR 34, 35 Power supply for right channel H-bridge, not connected to PVCCL or AVCC RINN 2 I Negative audio input for right channel. Biased at VREG/2. 6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated |
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Podobny opis - TPA3100D2IRGZRQ1 |
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