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ISL2671286IBZ Arkusz danych(PDF) 11 Page - Intersil Corporation |
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ISL2671286IBZ Arkusz danych(HTML) 11 Page - Intersil Corporation |
11 / 15 page ISL2671286 11 FN7863.0 November 1, 2011 Functional Description The ISL2671286 is based on a successive approximation register (SAR) architecture utilizing capacitive charge redistribution digital-to-analog converters (DACs). Figure 26 shows a simplified representation of the converter. During the acquisition phase (ACQ), the differential input is stored on the sampling capacitors (CS). The comparator is in a balanced state since the switch across its inputs is closed. The signal is fully acquired after tACQ has elapsed, and the switches then transition to the conversion phase (CONV) so the stored voltage can be converted to digital format. The comparator becomes unbalanced when the differential switch opens and the input switches transition (assuming that the stored voltage is not exactly at mid-scale). The comparator output reflects whether the stored voltage is above or below mid-scale, which sets the value of the MSB. The SAR logic then forces the capacitive DACs to adjust up or down by one-quarter of full-scale by switching in binarily weighted capacitors. Again, the comparator output reflects whether the stored voltage is above or below the new value and sets the value of the next lowest bit. This process repeats until all 12 bits have been resolved. ADC Transfer Function The output coding for the ISL2671286 is straight binary. The first code transition occurs at successive LSB values (i.e., 1 LSB, 2 LSB, and so on). The LSB size is VREF/4096. The ideal transfer characteristic of the ISL2671286 is shown in Figure 27. Analog Input The ISL2671286 features a pseudo-differential input with a nominal full-scale range equal to the applied VREF voltage. The negative input (VIN–) must be biased within 200mV of ground. Modes of Operation There are two possible modes of operation, which are controlled by the CS/SHDN signal. When CS/SHDN is high (deasserted), the ADC is in static mode. Conversely, when CS/SHDN is low (asserted), the device is in dynamic mode. There is no minimum or maximum number of SCLK cycles required to enter static mode. This simplifies power management and allows the user to easily optimize power dissipation versus throughput for various application requirements. DYNAMIC MODE This mode is entered when a conversion result is desired by asserting CS/SHDN. Figure 28 shows the general operation in this mode. The conversion is initiated on the falling edge of CS/SHDN (refer to “Serial Digital Interface” section). When CS/SHDN is deasserted, the conversion is terminated, and DOUT returns to a high-impedance state. Sixteen serial clock cycles are required to complete the conversion and access the complete conversion result. CS/SHDN may idle high until the next conversion or idle low until sometime prior to the next conversion. Once a data transfer is complete (DOUT has returned to a high-impedance state), another conversion can be initiated by again asserting CS/SHDN. STANDBY MODE The ISL2671286 enters the power-saving static mode automatically any time CS/SHDN is deasserted. The user is not required to force a device into this mode following a conversion in order to optimize power consumption. SHORT CYCLING In cases where a lower resolution conversion is acceptable, CS/SHDN can be pulled high before 12 SCLK falling edges have elapsed. This is referred to as short cycling, and it can be used to further optimize power dissipation. In this mode, a lower resolution result is acquired, but the ADC enters static mode sooner and exhibits a lower average power dissipation than if the complete conversion cycle is carried out. The acquisition time (tACQ) requirement must be met for the next conversion to be valid. POWER-ON RESET The ISL2671286 performs a power-on reset that requires approximately 2.5ms to execute when the supplies are first FIGURE 26. SAR ADC ARCHITECTURAL BLOCK DIAGRAM VIN+ VIN– VREF ACQ CONV ACQ ACQ CONV CONV SAR LOGIC 1LSB = VREF/4096 000...000 000...001 000...010 011...111 100...000 100...001 111...110 111...111 ANALOG INPUT +IN –(–IN) +½LSB +VREF – 1½LSB 0V +VREF – 1LSB FIGURE 27. IDEAL TRANSFER CHARACTERISTICS SCLK DOUT CSB 10 116 4 LEADING ZEROS AND CONVERSION RESULT FIGURE 28. NORMAL MODE OPERATION |
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