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ISLA216S25IR48EV1Z Arkusz danych(PDF) 9 Page - Intersil Corporation

Numer części ISLA216S25IR48EV1Z
Szczegółowy opis  16-Bit, 250/200/130 MSPS JESD204B High Speed Serial Output ADC
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Producent  INTERSIL [Intersil Corporation]
Strona internetowa  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISLA216S25IR48EV1Z Arkusz danych(HTML) 9 Page - Intersil Corporation

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ISLA216S
9
FN7996.0
February 2, 2012
Differential Output Voltage (Note 13)
760
mVP-P
SPI INTERFACE (Notes 14, 15)
SCLK Period
t
CLK
Write Operation
7
cycles
tCLK
Read Operation
16
cycles
CSB
↓ to SCLK↑ Setup Time
tS
Read or Write
2
cycles
CSB
↑ after SCLK↑ Hold Time
tH
Read or Write
5
cycles
Data Valid to SCLK
↑ Setup Time
tDS
Read or Write
6
cycles
Data Valid after SCLK
↑ Hold Time
tDH
Read or Write
4
cycles
Data Valid after SCLK
↓ Time
tDVR
Read
4
cycles
NOTES:
11. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending
on desired function.
12. The synchronous clock divider reset function is available as a (SPI-programmable) overload on the SYNC input.
13. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak single-ended swing is 1/2 of the differential swing.
14. The SPI interface timing is directly proportional to the ADC sample period (tS). Values above reflect multiples of a 4ns sample period, and must be
scaled proportionally for lower sample rates. ADC sample clock must be running for SPI communication.
15. The SPI may operate asynchronously with respect to the ADC sample clock.
Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
CONDITION
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C,
AIN =-2dBFS, fIN = 105MHz, fSAMPLE = 250MSPS.
FIGURE 3. SNR AND SFDR vs fIN
FIGURE 4. HD2 AND HD3 vs fIN
50
55
60
65
70
75
80
85
90
95
0
100
200
300
400
500
600
700
INPUT FREQUENCY (MHz)
SFDR AT 200 MSPS
SFDR AT 250 MSPS
SFDR AT 130 MSPS
SNR AT 250 MSPS
SNR AT 200 MSPS
SNR AT 130 MSPS
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
0
100
200
300
400
500
600
700
INPUT FREQUENCY (MHz)
HD2 AT 200 MSPS
HD2 AT 250 MSPS
HD2 AT 130 MSPS
HD3 AT 250 MSPS
HD3 AT 200 MSPS
HD3 AT 130 MSPS


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