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MC74VHCT74AD Arkusz danych(PDF) 1 Page - ON Semiconductor

Numer części MC74VHCT74AD
Szczegółowy opis  Dual D-Type Flip-Flop with Set and Reset
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Producent  ONSEMI [ON Semiconductor]
Strona internetowa  http://www.onsemi.com
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© Semiconductor Components Industries, LLC, 2009
November, 2009 − Rev. 6
1
Publication Order Number:
MC74VHCT74A/D
MC74VHCT74A
Dual D-Type Flip-Flop
with Set and Reset
The MC74VHCT74A is an advanced high speed CMOS D−type
flip−flop fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
The signal level applied to the D input is transferred to Q output
during the positive going transition of the Clock pulse.
Reset (RD) and Set (SD) are independent of the Clock (CP) and are
accomplished by setting the appropriate input Low.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
The VHCT74A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when VCC = 0 V. These
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
Features
High Speed: fmax = 60 MHz (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 4.5 V to 5.5 V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 128 FETs or 32 Equivalent Gates
Pb−Free Packages are Available
Figure 2. Logic Diagram
RD1
D1
CP1
SD1
RD2
D2
CP2
SD2
1
2
3
4
13
12
11
10
5
6
9
8
Q1
Q1
Q2
Q2
http://onsemi.com
Figure 1. Pin Assignment
SD1
CP1
D1
RD1
11
12
13
14
8
9
10
5
4
3
2
1
7
6
SD2
CP2
D2
RD2
VCC
Q2
Q2
GND
Q1
Q1
See detailed ordering and shipping information on page 3 of
this data sheet.
ORDERING INFORMATION
1
1
1
14
VHCT74AG
AWLYWW
1
14
VHCT
74A
ALYWG
G
MARKING DIAGRAMS
SOIC−14
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
FUNCTION TABLE
Inputs
Outputs
SD
RD
CP
D
Q
Q
LH
X
X
HL
HL
X
X
LH
L
L
X
X
H*
H*
HH
H
H
L
HH
L
L
H
H
H
L
X
No Change
H
H
H
X
No Change
H
H
X
No Change
*Both outputs will remain high as long as Set and Reset
are low, but the output states are unpredictable if Set
and Reset go high simultaneously.
A
= Assembly Location
WL, L
= Wafer Lot
Y
= Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)


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