LC75879PT

No.A1687-11/35

(2) When CL is stopped at the low level

Note: DD is the direction data.

• CCB address ……………….. “45H”

• D1 to D207 ……………….... Display data

• PS10, PS11, PS2 to PS4 ….... General-purpose output port (P1 to P4) function setting control data

• EXF ………………………... External clock operating frequency setting control data

• DN …………………………. S68 pin and S69/OSCI pin state setting control data

• OC …………………………. Internal oscillator operating mode/external clock operating mode switching control data

• P0 to P3 ……………………. Segment output port/general-purpose output port switching control data

• DT …………………………. 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data

• SC ………………………….. Segment on/off control data

• BU …………………………. Normal mode/power-saving mode control data

• PF0 to PF3 …………………. PWM output waveform frame frequency setting control data

• FC0 to FC2 ………………… Common/segment output waveform frame frequency setting control data

• CT0 to CT2 ………………… Display contrast setting control data

• W10 to W15, W20 to W25, ... PWM data of the PWM output

W30 to W35

B1

B0

D2

D1

0

1

D66

EXF

PS4

DD

2bits

Control data

17 bits

DI

CL

CE

0

0

0

D69

1

0

1

B3

B2

A1

A0

A3

A2

D67

0

0

PS10

PS3

PS11

SC

DT

P0

OC

0

0

BU

DN

PS2

P1 P2 P3

D68

D63 D64 D65

D62

D61

D60

B1

B0

D71

D70

0

1

D135

PF0

0

DD

2bits

Control data

14 bits

0

0

0

D138

1

0

1

B3

B2

A1

A0

A3

A2

D136

D140

D139

D141

0

0

CT1

CT0

PF3

PF2

1

0

CT2

PF1

0

FC0 FC1 FC2

D137

D132 D133 D134

D131

D130

D129

B1

B0

D143

D142

0

1

D207

W22

W21

DD

2bits

Control data

20 bits

0

0

0

W10

1

0

1

B3

B2

A1

A0

A3

A2

0

W12

W11

W13

W20

W14

W34

W33

W25

W24

0

1

W35

W23

W15

W30 W31 W32

0

D204 D205 D206

D203

D202

D201

Display data

69 bits

CCB address

8 bits

Display data

72 bits

CCB address

8 bits

Display data

66 bits

CCB address

8 bits