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FIN224ACMLX Arkusz danych(PDF) 6 Page - Fairchild Semiconductor

Numer części FIN224ACMLX
Szczegółowy opis  22-Bit Bi-Directional Serializer/Deserializer
Download  19 Pages
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Producent  FAIRCHILD [Fairchild Semiconductor]
Strona internetowa  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

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© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN224AC Rev.1.1.6
6
Serializer Operation Mode
The serializer configurations are described in the follow-
ing sections. The basic serialization circuitry works
essentially identically in these modes, but the actual data
and clock streams differ depending on if CKREF is the
same as the STROBE signal or not. When it is stated
that CKREF does not equal STROBE, each signal is dis-
tinct and CKREF must be running at a frequency high
enough to avoid any loss of data condition. CKREF must
never be a lower frequency than STROBE.
Serializer Operation: MODE 1 or MODE 2,
DIRI = 1, CKREF = STROBE
The PLL must receive a stable CKREF signal to achieve
lock prior to any valid data being sent. The CKREF sig-
nal can be used as the data STROBE signal provided
that data can be ignored during the PLL lock phase.
Once the PLL is stable and locked, the device can begin
to capture and serialize data. Data is captured on the ris-
ing edge of the STROBE signal and serialized. When
operating in serializer mode, the internal deserializer cir-
cuitry is disabled; including the serial clock, serial data
input buffers, bi-directional parallel outputs, and CKP
word clock. The CKP word clock is driven HIGH.
Serializer Operation: DIRI = 1, CKREF Does Not
= STROBE
If the same signal is not used for CKREF and STROBE,
the CKREF signal must be run at a higher frequency
than the STROBE rate to serialize the data correctly. The
actual serial transfer rate remains at 13 times the
CKREF frequency. A data bit value of zero is sent when
no valid data is present in the serial bit stream. The oper-
ation of the serializer otherwise remains the same.
The exact frequency that the reference clock needs to
run at depends upon the stability of the CKREF and
STROBE signal. If the source of the CKREF signal
implements spread spectrum technology, the minimun
frequency of the spread spectrum clock should be used
in calculating the ratio of STROBE frequency to the
CKREF frequency. Similarly, if the STROBE signal has
significant cycle-to-cycle variation, the maximum cycle-
to-cycle time needs to be factored into the selection of
the CKREF frequency.
Serializer Operation: MODE 3 (S1 = S2 =1),
DIRI =1. CKREF Divide by 2 Mode.
When operating in mode 3, the effective serial speed is
divided by two. This mode has been implemented to
accommodate cases where the reference clock fre-
quency is high compared to the actual strobe frequency.
The actual strobe frequency must be less than or equal
to 50% of the CKREF frequency for this mode to work
properly. This mode, in all other ways, operates the
same as described in the section where CKREF does
not equal STROBE.
Serializer Operation: DIRI = 1, No CKREF
A third method of serialization can be acheived by pro-
viding a free-running bit clock on the CKSI signal. This
mode is enabled by grounding the CKREF signal and
driving the DIRI signal HIGH. At power-up, the device is
configured to accept a serialization clock from CKSI. If a
CKREF is received, this device enables the CKREF seri-
alization mode. The device remains in this mode even if
CKREF is stopped. To re-enable this mode, the device
must be powered down and then powered back up with a
“logic 0” on CKREF.
Deserializer Operation Mode
The operation of the deserializer is dependent on the
data received on the DSI data signal pair and the CKSI
clock signal pair. The following sections describe the
operation of the deserializer under distinct serializer
source conditions. References to the CKREF and
STROBE signals refer to the signals associated with the
serializer device generating the serial data and clock sig-
nals that are inputs to the deserializer. When operating in
deserializer mode, the internal serializer circuitry is dis-
abled, including the parallel data input buffers. If there is
a CKREF signal provided, the CKSO serial clock contin-
ues to transmit bit clocks. Upon power-up (S1 or S2 = 1),
deserializer output data pins are driven LOW until valid
data is passed through the deserializer.
Deserializer Operation: DIRI = 0 (Serializer
Source: CKREF = STROBE)
When the DIRI signal is asserted LOW, the device is
configured as a deserializer. Data is captured on the
serial port and deserialized through use of the bit clock
sent with the data.
Deserializer Operation: DIRI = 0 (Serializer
Source: CKREF Does Not = STROBE)
The logical operation of the deserializer remains the
same if the CKREF is equal in frequency to the STROBE
or at a higher frequency than the STROBE. The actual
serial data stream presented to the deserializer is differ-
ent because it has non-valid data bits sent between
words. The duty cycle of CKP varies based on the ratio
of the frequency of the CKREF signal to the STROBE
signal. The frequency of the CKP signal is equal to the
STROBE frequency. In modes 1 and 2, the CKP LOW
time equals half of the CKREF period of the serializer. In
mode 3, the CKP LOW is equal to the CKREF period.
The CKP HIGH time is approximately equal to the
STROBE period, minus the CKP LOW time.


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