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FIN224CMLX Arkusz danych(PDF) 2 Page - Fairchild Semiconductor |
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FIN224CMLX Arkusz danych(HTML) 2 Page - Fairchild Semiconductor |
2 / 9 page © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN224C • Rev. 1.0.9 2 Pin Configuration Pin Name Description STROBE LVCMOS Strobe Signal for Latching Data into the Serializer (On Rising Edge) CKREF LVCMOS Clock Input and PLL Reference CKP LVCMOS Word Clock Output DP[24:1] LVCMOS Data I/O /DIRO LVCMOS Control Output Inversion of DIRI S1, S2 LVCMOS Select Pins, Controls the Mode of Operation, see Table 1 DIRI LVCMOS Control, Selects Serializer or Deserializer Mode 0 Deserializer 1 Serializer DSO+ / DSI- DSO- / DSI+ Serial Data I/O CKSI+, CKSI- Serial Clock Input CKSO+, CKSO- Serial Clock Output VDDP Power Supply for Parallel I/O and Internal Circuitry VDDS Power Supply for Serial I/O VDDA Power Supply for Core GND Ground Pins Note: 1. 0 = VIL; 1 = VIH. GND PAD Must be Grounded DP[9] /DIRO CKSO+ CKSO- DSO+ / DSI- DSO- / DSI+ CKSI- CKSI+ 1 DP[10] 2 4 DP[11] DP[12] 3 VDDP 5 CKP 6 DP[13] 7 DP[14] 8 26 27 25 29 24 23 28 30 DP[15] 9 DP[16] 10 S2 VDDS 22 21 DIRI GND PAD Must be Grounded DP[9] /DIRO CKSO+ CKSO- DSO+ / DSI- DSO- / DSI+ CKSI- CKSI+ 1 DP[10] 2 4 DP[11] DP[12] 3 VDDP 5 CKP 6 DP[13] 7 DP[14] 8 26 27 25 29 24 23 28 30 DP[15] 9 DP[16] 10 S2 VDDS 22 21 DIRI Figure 2. MLP-40 Pinout (Through View) |
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