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FIN3385MTDX Arkusz danych(PDF) 1 Page - Fairchild Semiconductor |
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FIN3385MTDX Arkusz danych(HTML) 1 Page - Fairchild Semiconductor |
1 / 21 page March 2012 © 2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN3385 / FIN3386 • Rev. 1.0.6 FIN3385 / FIN3386 Low-Voltage, 28-Bit, Flat-Panel Display Link Serializer / Deserializer Features Operation -40°C to +85°C Low Power Consumption 20MHz to 85MHz Shift Clock Support ±1V Common-Mode Range around 1.2V Narrow Bus Reduces Cable Size and Cost High Throughput (up to 2.38Gbps) Internal PLL with No External Component Compatible with TIA/EIA-644 Specification 56-Lead, TSSOP Package Description The FIN3385 and FIN3386 transform 28-bit wide parallel Low-Voltage TTL (LVTTL) data into four serial Low Voltage Differential Signaling (LVDS) data streams. A phase-locked transmit clock is transmitted in parallel with the data stream over a separate LVDS link. Every cycle of transmit clock, 28-bits of input LVTTL data are sampled and transmitted. The FIN3386 receives and converts the 4/3 serial LVDS data streams back into 28/21 bits of LVTTL data, acting as the deserializer. For the FIN3385, at a transmit clock frequency of 85MHz, 28-bits of LVTTL data are transmitted at a rate of 595Mbps per LVDS channel. This pair solves EMI and cable size problems associated with wide and high-speed TTL interfaces. Ordering Information Part Number Operating Temperature Range Package Packing Method FIN3385MTDX -40 to +85°C 56-Lead Thin-Shrink Small-Outline Package (TSSOP), JEDEC MO-153,6.1mm Wide Tape and Reel FIN3386MTDX |
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