Zakładka z wyszukiwarką danych komponentów
  Polish  ▼
ALLDATASHEET.PL

X  

AD7010ARS Arkusz danych(PDF) 7 Page - Analog Devices

Numer części AD7010ARS
Szczegółowy opis  CMOS JDC p/4 DQPSK Baseband Transmit Port
Download  8 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD7010ARS Arkusz danych(HTML) 7 Page - Analog Devices

  AD7010ARS Datasheet HTML 1Page - Analog Devices AD7010ARS Datasheet HTML 2Page - Analog Devices AD7010ARS Datasheet HTML 3Page - Analog Devices AD7010ARS Datasheet HTML 4Page - Analog Devices AD7010ARS Datasheet HTML 5Page - Analog Devices AD7010ARS Datasheet HTML 6Page - Analog Devices AD7010ARS Datasheet HTML 7Page - Analog Devices AD7010ARS Datasheet HTML 8Page - Analog Devices  
Zoom Inzoom in Zoom Outzoom out
 7 / 8 page
background image
AD7010
REV. B
–7–
Ramp-Up/Down Envelope Logic
The AD7010 provides on-chip envelope shaping logic, providing
power shaping control for the beginning and end of a transmit
burst. When BIN (Burst In) is brought high, the modulator is
reset to a transmitting all zeros state (i.e., Xk = Yk = 0) and
continues to transmit all zeros for the first two symbols, during
which the ramp-up envelope goes from zero to full scale as illus-
trated in Figure 10. The next symbol to be transmitted is [I1,
Q1], which represents the first two data bits clocked in after
BIN going high, i.e., [X1, Y1].
1
2
1
2
CO S
π
t
2T
1
2
+
1
2
CO S
π
t
2T
2 SYMBOLS
2 SYMBOLS
Figure 10. Ramp Envelope
When BIN is brought low, indicating the end of a transmit
burst, the current Di-bit symbol [XN+4, YN+4] that the AD7010
is receiving will be the last symbol to be computed for the 4
symbol ramp-down sequence. Also the N
th symbol is the last
active symbol prior to ramping down.
However, because the impulse response is equal to
±4 symbols,
four additional symbols are required to fully compute the analog
outputs when transmitting the (N+4)
th symbol. Hence there will
be eight subsequent TxCLKs, latching four additional Di-bit
symbols: [XN+5, YN+5] to [XN+8, XN+8].
As Figure 11 illustrates, the ramp-down envelope reaches zero
after two symbols, hence the third and fourth symbols do not
actually get transmitted.
Reconstruction Filters
The reconstruction filters smooth the DAC output signals, pro-
viding continuous time I and Q waveforms at the output pins.
These are 4th order Bessel low-pass filters with a –3 dB fre-
quency of approximately 22 kHz, the frequency response is
illustrated in Figure 12. The filters are designed to have a linear
phase response in the passband and due to the reconstruction
filters being on-chip, the phase mismatch between the I and Q
transmit channels is kept to a minimum.
0
–40
–80
1
1000
100
10
0.1
–60
–20
–30
–50
–70
–10
FREQUENCY – kHz
Figure 12. Reconstruction Filter Frequency Response for
I and Q DACs, MCLK = 2.688 MHz
Transmit Section Digital Interface
MODE1 = MODE2 = DGND: Digital
π/4 DQPSK Mode
Figures 5 and 6 show the timing diagrams for the transmit
interface when operating in JDC
π/4 DQPSK mode. Power is
sampled on the rising edge of MCLK. When Power is brought
high, the transmit section is brought out of sleep mode and ini-
tiates a self-calibration routine as described above. Once the
self-calibration is complete, the READY signal goes high to
indicate that a transmit burst can now begin. BIN (Burst in) is
brought high to initiate a transmit burst and should only be
brought high if the READY signal is already high.
X
1
Y
1
X
N
Y
N
Y
N+1
X
N+1
Y
N+2
X
N+2
Y
N+3
X
N+3
Y
N+4
X
N+4
2 SYMBOL
RAMP-UP ENVELOPE
2 SYMBOL
RAMP-DOWN ENVELOPE
I
1
Q
1
I
N
Q
N
I
N+1
Q
N+1
I
N+2
Q
N+2
I
N+3
Q
N+3
I
N+4
Q
N+4
0
0
0
0
SYMBOL
PHASE MAX
EFFECT
BIN
TxCLK
TxDATA
BOUT
(ITx–ITx),
(QTx–QTx)
Y
N+5
X
N+5
Y
N+6
X
N+6
Y
N+7
X
N+7
Y
N+8
X
N+8
= 480
t
1
Figure 11. Transmit Burst


Podobny numer części - AD7010ARS

ProducentNumer częściArkusz danychSzczegółowy opis
logo
Analog Devices
AD7010 AD-AD7010_15 Datasheet
170Kb / 8P
   CMOS JDC 4 DQPSK Baseband Transmit Port
REV. B
More results

Podobny opis - AD7010ARS

ProducentNumer częściArkusz danychSzczegółowy opis
logo
Analog Devices
AD7010 AD-AD7010_15 Datasheet
170Kb / 8P
   CMOS JDC 4 DQPSK Baseband Transmit Port
REV. B
AD7011 AD-AD7011 Datasheet
389Kb / 12P
   CMOS, ADC p/4 DQPSK Baseband Transmit Port
REV. B
AD7011 AD-AD7011_15 Datasheet
393Kb / 12P
   CMOS, ADC 4 DQPSK Baseband Transmit Port
REV. B
AD7013 AD-AD7013_15 Datasheet
456Kb / 20P
   CMOS TIA IS-54 Baseband Receive Port
REV. A
AD7013 AD-AD7013 Datasheet
591Kb / 20P
   CMOS TIA IS-54 Baseband Receive Port
REV. A
logo
California Micro Device...
G8912B CALMIRCO-G8912B Datasheet
373Kb / 8P
   CMOS PCM Transmit/receive Filters
logo
Sony Corporation
CXL5520M SONY-CXL5520M Datasheet
120Kb / 9P
   CMOS-CCD Baseband 1H Delay Line
logo
Skyworks Solutions Inc.
RFX2402E SKYWORKS-RFX2402E Datasheet
681Kb / 7P
   CMOS 2.4GHZ TRANSMIT/RECEIVE WLAN RFeIC
logo
Analog Devices
AD7001 AD-AD7001 Datasheet
619Kb / 16P
   LC2MOS GSM Baseband I/O Port
REV. A
AD7002 AD-AD7002 Datasheet
455Kb / 16P
   LC2MOS GSM Baseband I/O Port
REV. B
More results


Html Pages

1 2 3 4 5 6 7 8


Arkusz danych Pobierz

Go To PDF Page


Link URL




Polityka prywatności
ALLDATASHEET.PL
Czy Alldatasheet okazała się pomocna?  [ DONATE ] 

O Alldatasheet   |   Reklama   |   Kontakt   |   Polityka prywatności   |   Linki   |   Lista producentów
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com