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AD722JR-16-REEL7 Arkusz danych(PDF) 1 Page - Analog Devices |
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AD722JR-16-REEL7 Arkusz danych(HTML) 1 Page - Analog Devices |
1 / 12 page a RGB to NTSC/PAL Encoder AD722 © Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 FEATURES Low Cost, Integrated Solution +5 V Operation Accepts FSC Clock or Crystal, or 4FSC Clock Composite Video and Separate Y/C (S-Video) Outputs Minimal External Components: No External Filters or Delay Lines Required Onboard DC Restoration Accepts Either HSYNC & VSYNC or CSYNC Phase Lock to External Subcarrier Drives 75 Ω Reverse-Terminated Loads Logic Selectable NTSC or PAL Encoding Modes Compact 16-Pin SOIC APPLICATIONS RGB to NTSC or PAL Encoding PRODUCT DESCRIPTION The AD722 is a low cost RGB to NTSC/PAL Encoder that converts red, green and blue color component signals into their corresponding luminance (baseband amplitude) and chromi- nance (subcarrier amplitude and phase) signals in accordance with either NTSC or PAL standards. These two outputs are also combined to provide composite video output. All three out- puts can simultaneously drive 75 Ω, reverse-terminated cables. All logical inputs are CMOS compatible. The chip operates from a single +5 V supply. No external delay lines or filters are required. The AD722 may be powered down when not in use. The AD722 accepts either FSC or 4FSC clock. When a clock is not available, a low cost parallel-resonant crystal (3.58 MHz (NTSC) or 4.43 MHz (PAL)) and the AD722’s on-chip oscilla- tor generate the necessary subcarrier clock. The AD722 also ac- cepts the subcarrier clock from an external video source. The interface to VGA Controllers and MPEG Video Decoders is simple: an on-chip logic “XNOR” accepts the available verti- cal (VSYNC) and horizontal sync (HSYNC) signals and creates the composite sync (CSYNC) signal on-chip. If available, the AD722 will also accept a standard CSYNC signal by connecting VSYNC to +5 V and applying CSYNC to HSYNC pin. The AD722 contains decoding logic to identify valid HSYNC pulses for correct burst insertion. Delays in the U and V chroma filters are matched by an on-chip sampled-data delay line in the Y signal path. To prevent aliasing, a prefilter at 5 MHz is included ahead of the delay line and a post-filter at 5 MHz is added after the delay line to sup- press harmonics in the output. These low-pass filters are opti- mized for minimum pulse overshoot. The overall luma delay, relative to chroma, has been designed to be 170 ns, which precompensates for delays in the filters used in the IF section of a television receiver. This precompensation delay is already present in TV broadcasts. The AD722 comes in a space-saving SOIC and is specified for the 0 °C to +70°C commercial tem- perature range. FUNCTIONAL BLOCK DIAGRAM PHASE DETECTOR CHARGE PUMP FILTER LOOP XOSC 4FSC VCO SYNC SEPARATOR XNOR XOSC CHARGE PUMP FILTER LOOP 4FSC VCO XNOR 4FSC 4FSC FSC SUB- CARRIER NTSC/PAL HSYNC VSYNC BURST QUADRATURE +4 DECODER ±180° (PAL ONLY) NTSC/PAL FSC 90 ° FSC 0 ° 4FSC SC 90 °/270° FSC CSYNC CSYNC DC CLAMP RED GREEN BLUE RGB-TO-YUV ENCODING MATRIX BURST Y 3-POLE LP PRE- FILTER U V 4-POLE LPF 4-POLE LPF BALANCED MODULATORS 3-POLE LPF 3.6MHz (NTSC) 4.4MHz (PAL) NTSC/PAL CSYNC INSERTION SAMPLED- DATA DELAY LINE 2-POLE LP POST- FILTER X2 X2 X2 LUMINANCE OUTPUT COMPOSITE OUTPUT CHROMINANCE OUTPUT U CLAMP V CLAMP NTSC/PAL CLOCK AT 4FSC DC CLAMP DC CLAMP REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. |
Podobny numer części - AD722JR-16-REEL7 |
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Podobny opis - AD722JR-16-REEL7 |
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