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AD7226KR Arkusz danych(PDF) 8 Page - Analog Devices |
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AD7226KR Arkusz danych(HTML) 8 Page - Analog Devices |
8 / 12 page AD7226 REV. A –8– Unipolar Output Operation This is the basic mode of operation for each channel of the AD7226, with the output voltage having the same positive polarity as +VREF. The AD7226 can be operated single supply (VSS = AGND) or with positive/negative supplies (see op-amp section which outlines the advantages of having negative VSS). The code table for unipolar output operation is shown in Table II. Note that the voltage at VREF must never be negative with re- spect to DGND in order to prevent parasitic transistor turn-on. Connections for the unipolar output operation are shown in Fig- ure 12. Figure 12. AD7226 Unipolar Output Circuit Table II. Unipolar Code Table DAC Latch Contents MSB LSB Analog Output 1 1 1 1 1 1 1 1 +V REF 255 256 1 0 0 0 0 0 0 1 +V REF 129 256 1 0 0 0 0 0 0 0 +V REF 128 256 =+ V REF 2 0 1 1 1 1 1 1 1 +V REF 127 256 0 0 0 0 0 0 0 1 +V REF 1 256 0 0 0 0 0 0 0 0 0 V Note: 1 LSB = V REF () 2−8 ()=V REF 1 256 Bipolar Output Operation Each of the DACs of the AD7226 can be individually config- ured to provide bipolar output operation. This is possible using one external amplifier and two resistors per channel. Figure 13 shows a circuit used to implement offset binary coding (bipolar operation) with DAC A of the AD7226. In this case V OUT = 1 + R2 R1 ⋅ D AV REF () – R2 R1 ⋅ V REF () With R1 = R2 VOUT = (2 DA – 1) • VREF where DA is a fractional representation of the digital word in latch A. Mismatch between R1 and R2 causes gain and offset errors and therefore these resistors must match and track over temperature. Once again the AD7226 can be operated in single supply or from positive/negative supplies. Table III shows the digital code versus output voltage relationship for the circuit of Figure 13 with R1 = R2. Figure 13. AD7226 Bipolar Output Circuit Table III. Bipolar (Offset Binary) Code Table DAC Latch Contents MSB LSB Analog Output 1 1 1 1 1 1 1 1 +V REF 127 128 1 0 0 0 0 0 0 1 +V REF 1 128 1 0 0 0 0 0 0 0 0 V 0 1 1 1 1 1 1 1 –V REF 1 128 0 0 0 0 0 0 0 1 –V REF 127 128 0 0 0 0 0 0 0 0 –V REF 128 128 = –V REF AGND BIAS The AD7226 AGND pin can be biased above system GND (AD7226 DGND) to provide an offset “zero” analog output voltage level. Figure 14 shows a circuit configuration to achieve this for channel A of the AD7226. The output voltage, VOUTA, can be expressed as: VOUTA = VBIAS + DA (VIN) where DA is a fractional representation of the digital input word (0 ≤ D ≤ 255/256). |
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Podobny opis - AD7226KR |
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