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AD7226BQ Arkusz danych(PDF) 4 Page - Analog Devices |
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AD7226BQ Arkusz danych(HTML) 4 Page - Analog Devices |
4 / 12 page AD7226 REV. A –4– ABSOLUTE MAXIMUM RATINGS* VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V, VDD VSS to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V, VDD VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +24 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD + 0.3 V VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD VOUT to AGND 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD Power Dissipation (Any Package) to +75 °C . . . . . . . . 500 mW Derates above 75 °C by . . . . . . . . . . . . . . . . . . . . . 2.0 mW/°C Operating Temperature Commercial (K Version) . . . . . . . . . . . . . . –40 °C to +85°C Industrial (B Version) . . . . . . . . . . . . . . . . –40 °C to +85°C Extended (T Version) . . . . . . . . . . . . . . . –55 °C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . –65 °C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300 °C NOTES *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1Outputs may be shorted to AGND provided that the power dissipation of the package is not exceeded. Typically short circuit current to AGND is 60 mA. WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7226 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN CONFIGURATIONS DIP and SOIC LCCC PLCC TERMINOLOGY TOTAL UNADJUSTED ERROR This is a comprehensive specification which includes full-scale error, relative accuracy and zero code error. Maximum output voltage is VREF – 1 LSB (ideal), where 1 LSB (ideal) is VREF/ 256. The LSB size will vary over the VREF range. Hence the zero code error will, relative to the LSB size, increase as VREF de- creases. Accordingly, the total unadjusted error, which includes the zero code error, will also vary in terms of LSB’s over the VREF range. As a result, total unadjusted error is specified for a fixed reference voltage of +10 V. RELATIVE ACCURACY Relative Accuracy or endpoint nonlinearity, is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after al- lowing for zero and full-scale error and is normally expressed in LSB’s or as a percentage of full-scale reading. DIFFERENTIAL NONLINEARITY Differential Nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB max over the operating temperature range ensures monotonicity. DIGITAL CROSSTALK The glitch impulse transferred to the output of one converter due to a change in the digital input code to another of the con- verters. It is specified in nV secs and is measured at VREF = 0 V. FULL SCALE ERROR Full-Scale Error is defined as: Measured Value – Zero Code Error – Ideal Value |
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