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AD7226BQ Arkusz danych(PDF) 6 Page - Analog Devices |
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AD7226BQ Arkusz danych(HTML) 6 Page - Analog Devices |
6 / 12 page AD7226 REV. A –6– INTERFACE LOGIC INFORMATION Address lines A0 and A1 select which DAC will accept data from the input port. Table I shows the selection table for the four DACs with Figure 4 showing the input control logic. When the WR signal is LOW, the input latches of the selected DAC are transparent and its output responds to activity on the data bus. The data is latched into the addressed DAC latch on the rising edge of WR. While WR is high the analog outputs remain at the value corresponding to the data held in their respective latches. Table I. AD7226 Truth Table AD7226 Control Inputs AD7226 WR A1 A0 Operation H X X No Operation Device Not Selected L L L DAC A Transparent g L L DAC A Latched L L H DAC B Transparent g L H DAC B Latched L H L DAC C Transparent g H L DAC C Latched L H H DAC D Transparent g H H DAC D Latched L = Low State, H = High State, X = Don’t Care Figure 4. Input Control Logic Figure 5. Write Cycle Timing Diagram Typical Performance Characteristics (TA = 25 C, VDD = +15 V, VSS = –5 V) Figure 6. Channel-to-Channel Matching Figure 7. Relative Accuracy vs. VREF Figure 8. Differential Nonlinearity vs. VREF |
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