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AD7233AN Arkusz danych(PDF) 7 Page - Analog Devices |
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AD7233AN Arkusz danych(HTML) 7 Page - Analog Devices |
7 / 8 page AD7233 REV. A –7– MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD7233 is via a serial bus which uses standard protocol compatible with DSP processors and microcontrollers. The communications channel requires a three-wire interface consisting of a clock signal, a data signal and a synchronization signal. The AD7233 requires a 16-bit data word with data valid on the falling edge of SCLK. For all of the interfaces, the DAC update may be done automatically when all the data is clocked in or it may done under control of LDAC. Figures 5 to 8 show the AD7233 configured for interfacing to a number of popular DSP processors and microcontrollers. AD7233–ADSP-2101/ADSP-2102 Interface Figure 5 shows a serial interface between the AD7233 and the ADSP-2101/ADSP-2102 DSP processor. The ADSP-2101/ ADSP-2102 contains two serial ports, and either port may be used in the interface. The data transfer is initiated by TFS going low. Data from the ADSP-2101/ADSP-2102 is clocked into the AD7233 on the falling edge of SCLK. When the data transfer is complete TFS is taken high. In the interface shown the DAC is updated using an external timer which generates an LDAC pulse. This could also be done using a control or decoded ad- dress line from the processor. Alternatively, the LDAC input could be hardwired low, and in this case the automatic update mode is selected whereby the DAC update takes place automati- cally on the 16th falling edge of SCLK. TIMER LDAC ADSP-2101/ ADSP-2102* SDIN SCLK * ADDITIONAL PINS OMITTED FOR CLARITY SYNC SCLK DT AD7233* TFS Figure 5. AD7233 to ADSP-2101/ADSP-2102 Interface AD7233-DSP56000 Interface A serial interface between the AD7233 and the DSP56000 is shown in Figure 6. The DSP56000 is configured for Normal Mode Asynchronous operation with Gated Clock. It is also set up for a 16-bit word with SCK and SC2 as outputs and the FSL control bit set to a 0. SCK is internally generated on the DSP56000 and applied to the AD7233 SCLK input. Data from the DSP56000 is valid on the falling edge of SCK. The SC2 output provides the framing pulse for valid data. This line must be inverted before being applied to the SYNC input of the AD7233. The LDAC input of the AD7233 is connected to GND so the update of the DAC latch takes place automatically on the 16th falling edge of SCLK. An external timer could also be used as in the previous interface if an external update is required. LDAC DSP56000 SCLK SDIN SCK STD * ADDITIONAL PINS OMITTED FOR CLARITY AD7233* SC2 SYNC Figure 6. AD7233 to DSP56000 Interface AD7233–87C51 Interface A serial interface between the AD7233 and the 87C51 micro- controller is shown in Figure 7. TXD of the 87C51 drives SCLK of the AD7233 while RXD drives the serial data line of the part. The SYNC signal is derived from the port line P3.3. The 87C51 provides the LSB of its SBUF register as the first bit in the serial data stream. Therefore, the user will have to ensure that the data in the SBUF register is arranged correctly so that the don’t care bits are the first to be transmitted to the AD7233 and the last bit to be sent is the LSB of the word to be loaded to the AD7233. When data is to be transmitted to the part, P3.3 is taken low. Data on RXD is valid on the falling edge of TXD. The 87C51 transmits its serial data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. To load data to the AD7233, P3.3 is kept low after the first eight bits are transferred and a second byte of data is then transferred serially to the AD7233. When the second serial transfer is complete, the P3.3 line is taken high. Figure 7 shows the LDAC input of the AD7233 hardwired low. As a result, the DAC latch and the analog output will be up- dated on the sixteenth falling edge of TXD after the SYNC sig- nal for the DAC has gone low. Alternatively, the scheme used in previous interfaces, whereby the LDAC input is driven from a timer, can be used. LDAC 87C51* SDIN TXD * ADDITIONAL PINS OMITTED FOR CLARITY SYNC SCLK RXD AD7233* P3.3 Figure 7. AD7233 to 87C51 Interface |
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