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AD7224LR-18 Arkusz danych(PDF) 7 Page - Analog Devices |
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AD7224LR-18 Arkusz danych(HTML) 7 Page - Analog Devices |
7 / 8 page AD7224 REV. B –7– BIPOLAR OUTPUT OPERATION The AD7224 can be configured to provide bipolar output op- eration using one external amplifier and two resistors. Figure 6 shows a circuit used to implement offset binary coding. In this case V O = 1 + R2 R1 • D V REF () – R2 R1 • V REF () With R1 = R2 VO = (2 D – 1) • VREF where D is a fractional representation of the digital word in the DAC register. Mismatch between R1 and R2 causes gain and offset errors; therefore, these resistors must match and track over tempera- ture. Once again, the AD7224 can be operated in single supply or from positive/negative supplies. Table III shows the digital code versus output voltage relationship for the circuit of Figure 6 with R1 = R2. +15V +15V V REF R1 R2 V OUT R1, R2 = 10k Ω ±0.1% DAC DB7 DB0 3 V DD V REF CS WR LDAC RESET V SS AGND DGND AD7224 V OUT DATA (8-BIT) Figure 6. Bipolar Output Circuit Table III. Bipolar (Offset Binary) Code Table DAC Register Contents MSB LSB Analog Output 1 1 1 1 1 1 1 1 +V REF 127 128 1 0 0 0 0 0 0 1 +V REF 1 128 1 0 0 0 0 0 0 0 0 V 0 1 1 1 1 1 1 1 –V REF 1 128 0 0 0 0 0 0 0 1 –V REF 127 128 0 0 0 0 0 0 0 0 –V REF 128 128 = –V REF AGND BIAS The AD7224 AGND pin can be biased above system GND (AD7224 DGND) to provide an offset “zero” analog output voltage level. Figure 7 shows a circuit configuration to achieve this. The output voltage, VOUT, is expressed as: VOUT = VBIAS + D • (VIN) where D is a fractional representation of the digital word in DAC register and can vary from 0 to 255/256. For a given VIN, increasing AGND above system GND will re- duce the effective VDD–VREF which must be at least 4 V to en- sure specified operation. Note that VDD and VSS for the AD7224 must be referenced to DGND. DAC VDD VREF VSS AGND DGND AD7224 VOUT VIN VIN VBIAS Figure 7. AGND Bias Circuit MICROPROCESSOR INTERFACE 8085A 8088 A15 A8 ALE AD0 AD7 ADDRESS DECODE LATCH EN AD7224* WR DB7 DB0 LDAC WR ADDRESS BUS ADDRESS DATA BUS *LINEAR CIRCUITRY OMITTED FOR CLARITY CS Figure 8. AD7224 to 8085A/8088 Interface D0 D7 DATA BUS *LINEAR CIRCUITRY OMITTED FOR CLARITY E OR φ2 D0 D7 E OR φ2 R/W A15 A0 6809 6502 ADDRESS DECODE EN ADDRESS BUS LDAC WR CS DB7 DB0 AD7224* Figure 9. AD7224 to 6809/6502 Interface Z-80 A15 A0 D0 D7 AD7224* DB7 DB0 LDAC WR ADDRESS BUS DATA BUS *LINEAR CIRCUITRY OMITTED FOR CLARITY ADDRESS DECODE CS WR Figure 10. AD7224 to Z-80 Interface 68008 A23 A1 D0 D7 AD7224* DB7 DB0 LDAC WR ADDRESS BUS DATA BUS *LINEAR CIRCUITRY OMITTED FOR CLARITY ADDRESS DECODE CS R/W DTACK Figure 11. AD7224 to 68008 Interface |
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