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AD724JR Arkusz danych(PDF) 11 Page - Analog Devices |
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AD724JR Arkusz danych(HTML) 11 Page - Analog Devices |
11 / 15 page AD724 REV. B –11– video from an MPEG decoder and creating both analog RGB video and composite video. The 24-bit wide RGB video is converted to analog RGB by the ADV7120 (Triple 8-bit video DAC—available in 48-lead LQFP). The analog current outputs from the DAC are termi- nated to ground at both ends with 75 Ω as called for in the data sheet. These signals are ac coupled to the analog inputs of the AD724. The HSYNC and VSYNC signals from the MPEG Controller are directly applied to the AD724. If the set of termination resistors closest to the AD724 are re- moved, an RGB monitor can be connected to these signals and will provide the required second termination. This is acceptable as long as the RGB monitor is always present and connected. If it is to be removed on occasion, another termination scheme is required. The AD8013 or AD8073 triple video op amp can provide buff- ering for such applications. Each channel is set for a gain of two while the outputs are back terminated with a series 75 Ω resis- tor. This provides the proper signal levels at the monitor, which terminates the lines with 75 Ω. AD724 APPLICATION DISCUSSION—NTSC/PAL CRYSTAL SELECT CIRCUIT For systems that support both NTSC and PAL, and will use a crystal for the subcarrier, a low cost crystal selection circuit can be made that, in addition to the two crystals, requires two low cost diodes, two resistors and a logic inverter gate. The circuit selection can be driven by the STND signal that already drives Pin 1 to select between NTSC and PAL operation for the AD724. A schematic for such a circuit is shown in Figure 17. Each crys- tal ties directly to FIN (Pin 3) with one terminal and has the other terminal connected via a series diode to ground. Each diode serves as a switch, depending on whether it is forward biased or has no bias. FIN AGND DGND HSYNC VSYNC HSYNC VSYNC COMP 75 220 F COMPOSITE VIDEO CRMA LUMA 75 220 F 75 220 F S-VIDEO 10k AD724 ENCD SELECT STND APOS DPOS 0.1 F 0.01 F 10–30pF L1 (FERRITE BEAD) +5V (VAA) 10 F 33 F +5V (VCC) GND ADV7120 SYNC CLOCK BLANK GND 24 DATA IN HSYNC VSYNC +5V (VAA) 10k +5V 10k 0.1 F 0.01 F RSET 550 0.1 F +5V VAA VREF FSADJ COMP 0.1 F +5V (VAA) RIN GIN BIN 75 75 75 IOG IOR IOB +5V 10k AD589 (1.2V REF) +5V 0.1 F +5V CRYSTAL * PARALLEL–RESONANT CRYSTAL; 3.579545MHz (NTSC) OR 4.433620MHz (PAL) CAPACITOR VALUE DEPENDS ON CRYSTAL CHOSEN ** * 75 75 75 *** *** 0.1 F CAPACITORS RECOMMENDED **FSC OR 4FSC CLOCK; 3.579545MHz, 14.31818MHz (NTSC) OR 4.433620MHz, 17.734480MHz(PAL) OSC MPEG DECODER 0.1 F 0.1 F 0.1 F Figure 16. AD724 and ADV7120/ADV7122 Providing MPEG Video Solution Figure 15 shows a circuit for connection to the VGA port of a PC. The RGB outputs are ac coupled to the respective inputs of the AD724. These signals should each be terminated to ground with 75 Ω. The standard 15-pin VGA connector has HSYNC on Pin 13 and VSYNC on Pin 14. These signals also connect directly to the same name signals on the AD724. The FIN signal can be provided by any of the means described elsewhere in the data sheet. For a synchronous NTSC system, the internal 4FSC (14.31818 MHz) clock that drives the VGA controller can be used for FIN on the AD724. This signal is not directly accessible from outside the computer, but it does appear on the VGA card. If a separate RGB monitor is also to be used, it is not possible to simply connect it to the R, G and B signals. The monitor pro- vides a termination that would double terminate these signals. The R, G and B signals should be buffered by three amplifiers with high input impedances. These should be configured for a gain of two, which is normalized by the divide-by-two termina- tion scheme used for the RGB monitor. The AD8013 is a triple video amplifier that can provide the necessary buffering in a single package. It also provides a disable pin for each amplifier, which can be used to disable the drive to the RGB monitor when interlaced video is used (SELECT = LO). When the RGB signals are noninterlaced, setting SELECT HI will enable the AD8013 to drive the RGB monitor and disable the encoding function of the AD724 via Pin 5. HSYNC and VSYNC are logic level signals that can drive both the AD724 and RGB monitor in parallel. If the disable feature is not required, the AD8073 triple video op amp can provide a lower cost solution. AD724 Used with an MPEG Decoder MPEG decoding of compressed video signals is becoming a more prevalent feature in many PC systems. To display images on the computer monitor, video in RGB format is required. However, to display the images on a TV monitor, or to record the images on a VCR, video in composite format is required. Figure 16 shows a schematic for taking the 24-bit wide RGB |
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