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AD7249BN Arkusz danych(PDF) 10 Page - Analog Devices |
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AD7249BN Arkusz danych(HTML) 10 Page - Analog Devices |
10 / 12 page REV. C –10– AD7249 MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD7249 is via a serial bus which uses standard protocol compatible with DSP processors and microcontrollers. The communications channel requires a three-wire interface consisting of a clock signal, a data signal and a synchronization signal. The AD7249 requires a 16-bit data word with data valid on the falling edge of SCLK. For all the interfaces, the DAC update may be done automatically when all the data is clocked in or it may be done under control of LDAC. Figures 11 to 15 show the AD7249 configured for interfacing to a number of popular DSP processors and microcontrollers. AD7249–ADSP-2101/ADSP-2102 Interface Figure 11 shows a serial interface between the AD7249 and the ADSP-2101/ADSP-2102 DSP processor. The ADSP-2101/ ADSP-2102 contains two serial ports and either port may be used in the interface. The data transfer is initiated by TFS going low. Data from the ADSP-2101/ADSP-2102 is clocked into the AD7249 on the falling edge of SCLK. DB12 of the 16-bit serial data stream selects the DAC to be updated. Both DACs can be updated by holding LDAC high while performing two write cycles to the DAC. TFS must be taken high after each 16 bit write cycle. LDAC is brought low at the end of the second cycle and both DAC outputs are updated together. In the interface shown the DAC is updated using an external timer which generates an LDAC pulse. This could also be done using a control or decoded address line from the processor. Alterna- tively, if the LDAC input is hardwired low the output update takes place automatically on the 16th falling edge of SCLK. AD7249* ADSP-2101/ ADSP-2102* LDAC SCLK SDIN SYNC SCLK DT TFS TIMER *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 11. AD7249–ADSP-2101/ADSP-2102 Interface AD7249–DSP56000 Interface A serial interface between the AD7249 and the DSP56000 is shown in Figure 12. The DSP56000 is configured for Normal Mode Asynchronous operation with Gated Clock. It is also set up for a 16-bit word with SCK and SC2 as outputs and the FSL control bit set to a “0.” SCK is internally generated on the DSP56000 and applied to the AD7249 SCLK input. Data from the DSP56000 is valid on the falling edge of SCK. The SC2 output provides the framing pulse for valid data. This line must be inverted before being applied to the SYNC input of the AD7249. AD7249* DSP56000 LDAC SCLK SDIN SYNC SCK STD SC2 TIMER *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 12. AD7249–DSP56000 Interface In this interface an external LDAC pulse generated from an external timer is used to update the outputs of the DACs. This update can also be produced using a bit programmable control line from the DSP56000. AD7249–TMS32020 Interface Figure 13 shows a serial interface between the AD7249 and the TMS32020 DSP processor. In this interface, the CLKX and FSX signals for the TMS32020 should be generated using external clock/timer circuitry. The FSX pin of the TMS32020 must be configured as an input. Data from the TMS32020 is valid on the falling edge of CLKX. The clock/timer circuitry generates the LDAC signal for the AD7249 to synchronize the update of the output with the serial transmission. Alternatively, the automatic update mode may be selected by connecting LDAC to DGND. AD7249* TMS32020 LDAC SCLK SDIN SYNC FSX CLKX DX CLOCK/ TIMER *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 13. AD7249–TMS32020 Interface |
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