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AD725AR Arkusz danych(PDF) 4 Page - Analog Devices |
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AD725AR Arkusz danych(HTML) 4 Page - Analog Devices |
4 / 20 page REV. 0 –4– AD725 PIN DESCRIPTIONS Pin Mnemonic Description Equivalent Circuit 1 STND Encoding Standard Pin. A Logic HIGH input selects NTSC encoding. Circuit A A Logic LOW input selects PAL encoding. TTL Logic Levels. 2 AGND Analog Ground Connection. 3 4FSC 4FSC Clock Input. Circuit A For NTSC: 14.318 180 MHz. For PAL: 17.734 475 MHz. TTL Logic Levels. 4 APOS Analog Positive Supply (+5 V ± 5%). 5 CE Chip Enable. A Logic HIGH input enables the encode function. Circuit A A Logic LOW input powers down chip when not in use. TTL Logic Levels. 6 RIN Red Component Video Input. Circuit B 0 mV to 714 mV AC-Coupled. 7 GIN Green Component Video Input. Circuit B 0 mV to 714 mV AC-Coupled. 8 BIN Blue Component Video Input. Circuit B 0 mV to 714 mV AC-Coupled. 9 CRMA Chrominance Output.* Circuit C Approximately 1.8 V peak-to-peak for both NTSC and PAL. 10 COMP Composite Video Output.* Circuit C Approximately 2.5 V peak-to-peak for both NTSC and PAL. 11 LUMA Luminance plus CSYNC Output.* Circuit C Approximately 2 V peak-to-peak for both NTSC and PAL. 12 YTRAP Luminance Trap Filter Tap. Attach L-C resonant network to reduce cross-color artifacts. Circuit D 13 DGND Digital Ground Connection. 14 DPOS Digital Positive Supply (+5 V ± 5%). 15 VSYNC Vertical Sync Signal (if using external CSYNC set at > +2 V). TTL Logic Levels. Circuit A 16 HSYNC Horizontal Sync Signal (or CSYNC signal). TTL Logic Levels. Circuit A *The Luminance, Chrominance and Composite Outputs are at twice normal levels for driving 75 Ω reverse-terminated lines. 7 VCLAMP 6 8 DPOS DGND 3 1 5 15 16 DPOS DGND 10 9 11 APOS AGND DGND DPOS APOS AGND DGND DPOS 12 1k Circuit A Circuit B Circuit C Circuit D Figure 1. Equivalent Circuits |
Podobny numer części - AD725AR |
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Podobny opis - AD725AR |
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