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AD7247ATQ Arkusz danych(PDF) 9 Page - Analog Devices |
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AD7247ATQ Arkusz danych(HTML) 9 Page - Analog Devices |
9 / 12 page AD7237A/AD7247A REV. 0 –9– Figure 6. AD7237A Input Control Logic Table II. AD7237A Truth Table CS WR A1 A0 LDAC Function 1 X X X 1 No Data Transfer X 1 X X 1 No Data Transfer 0 0 0 0 1 DAC A LS Input Latch Transparent 0 0 0 1 1 DAC A MS Input Latch Transparent 0 0 1 0 1 DAC B LS Input Latch Transparent 0 0 1 1 1 DAC B MS Input Latch Transparent 1 1 X X 0 DAC A and DAC B DAC Latches Updated Simultaneously from the Respective Input Latches X = Don’t Care. However, care must be taken while exercising LDAC during a write cycle. If an LDAC operation overlaps a CS and WR op- eration, there is a possibility of invalid data being latched to the output. To avoid this, LDAC must remain low after CS or WR return high for a period equal to or greater than t8, the mini- mum LDAC pulse width. Figure 7. AD7237A Write Cycle Timing Diagram Table I. AD7247A Truth Table CSA CSB WR Function X X 1 No Data Transfer 1 1 X No Data Transfer 0 1 0 DAC A Latch Transparent 1 0 0 DAC B Latch Transparent 0 0 0 Both DAC Latches Transparent X = Don’t Care INTERFACE LOGIC INFORMATION—AD7237A The input loading structure on the AD7237A is configured for interfacing to microprocessors with an 8-bit-wide data bus. The part contains two 12-bit latches per DAC—an input latch and a DAC latch. Each input latch is further subdivided into a least significant 8-bit latch and a most significant 4-bit latch. Only the data held in the DAC latches determines the outputs from the part. The input control logic for the AD7237A is shown in Figure 6, while the write cycle timing diagram is shown in Figure 7. CS , WR, A0 and A1 control the loading of data to the input latches. The eight data inputs accept right-justified data. Data can be loaded to the input latches in any sequence. Provided that LDAC is held high, there is no analog output change as a result of loading data to the input latches. Address lines A0 and A1 determine which latch data is loaded to when CS and WR are low. The selection of the input latches is shown in the truth table for AD7237A operation in Table II. The LDAC input controls the transfer of 12-bit data from the input latches to the DAC latches. Both DAC latches, and hence both analog outputs, are updated at the same time. The LDAC signal is level triggered, and data is latched into the DAC latch on the rising edge of LDAC. The LDAC input is asynchronous and independent of WR. This is useful in many applications especially in the simultaneous updating of multiple AD7237As. |
Podobny numer części - AD7247ATQ |
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Podobny opis - AD7247ATQ |
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