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AD7248AAN Arkusz danych(PDF) 11 Page - Analog Devices

Numer części AD7248AAN
Szczegółowy opis  LC2MOS 12-Bit DACPORTs
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AD7245A/AD7248A
REV. A
–11–
BIPOLAR CONFIGURATION
The bipolar configuration for the AD7245A/AD7248A, which
gives an output voltage range from –5 V to +5 V, is achieved by
connecting the ROFS input to REF OUT and connecting RFB
and VOUT. The AD7245A/AD7248A must be operated from
dual supplies to achieve this output voltage range. The code
table for bipolar operation is shown in Table IV.
Table IV. Bipolar Code Table
DAC Latch Contents
MSB
LSB
Analog Output, VOUT
1 1 1 1
1 1 1 1
1 1 1 1
+VREF
×
2047
2048


1 0 0 0
0 0 0 0
0 0 0 1
+VREF
×
1
2048


1 0 0 0
0 0 0 0
0 0 0 0
0 V
0 1 1 1
1 1 1 1
1 1 1 1
–VREF
×
1
2048


0 0 0 0
0 0 0 0
0 0 0 1
–VREF
×
2047
2048


0 0 0 0
0 0 0 0
0 0 0 0
–VREF
×
2048
2048


= –V
REF
NOTE:
1 LSB = 2
× V
REF(2
–11) = V
REF
1
2048


AGND BIAS
The AD7245A/AD7248A AGND pin can be biased above sys-
tem GND (AD7245A/AD7248A DGND) to provide an offset
“zero” analog output voltage level. With unity gain on the am-
plifier (ROFS = VOUT = RFB) the output voltage, VOUT is ex-
pressed as:
VOUT = VBIAS + D
VREF
where D is a fractional representation of the digital word in the
DAC latch and VBIAS is the voltage applied to the AD7245A/
AD7248A AGND pin.
Because the current flowing out of the AGND pin varies with
digital code, the AGND pin should be driven from a low imped-
ance source. A circuit configuration is outlined for AGND bias
in Figure 9 using the AD589, a +1.23 V bandgap reference.
If a gain of 2 is used on the buffer amplifier the output voltage,
VOUT is expressed as
VOUT = 2(VBIAS + D
VREF)
In this case care must be taken to ensure that the maximum out-
put voltage is not greater than VDD –3 V. The VDD–VOUT over-
head must be greater than 3 V to ensure correct operation of the
part. Note that VDD and VSS for the AD7245A/AD7248A must
be referenced to DGND (system GND). The entire circuit can
be operated in single supply with the VSS pin of the AD7245A/
AD7248A connected to system GND.
Figure 9. AGND Bias Circuit
PROGRAMMABLE CURRENT SINK
Figure 10 shows how the AD7245A/AD7248A can be config-
ured with a power MOSFET transistor, the VN0300M, to pro-
vide a programmable current sink from VDD or VSOURCE. The
VN0300M is placed in the feedback of the AD7245A/
AD7248A amplifier. The entire circuit can be operated in single
supply by tying the VSS of the AD7245A/AD7248A to AGND.
The sink current, ISINK, can be expressed as:
ISINK =
D
×V
REF
R1
Figure 10. Programmable Current Sink
Using the VN0300M, the voltage drop across the load can typi-
cally be as large as VSOURCE –6 V) with VOUT of the DAC at
+5 V. Therefore, for a current of 50 mA flowing in the R1 (with
all 1s in the DAC register) the maximum load is 200
Ω with
VSOURCE = +15 V. The VN0300M can actually handle currents
up to 500 mA and still function correctly in the circuit, but in
practice the circuit must be used with larger values of VSOURCE
otherwise it requires a very small load.
Since the tolerance value on the reference voltage of the
AD7245A/AD7248A is
±0.2%, then the absolute value of I
SINK
can vary by
±0.2% from device to device for a fixed value of R1.
Because the input bias current of the AD7245A/AD7248A’s op
amp is only of the order of picoamps, its effect on the sink cur-
rent is negligible. Tying the ROFS input to RFB input reduces this
effect even further and prevents noise pickup which could occur
if the ROFS pin was left unconnected.


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