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AD7248AAQ Arkusz danych(PDF) 10 Page - Analog Devices |
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AD7248AAQ Arkusz danych(HTML) 10 Page - Analog Devices |
10 / 16 page AD7245A/AD7248A REV. A –10– the simultaneous updating of multiple AD7248A outputs. How- ever, in systems where the asynchronous LDAC can occur dur- ing a write cycle (or vice versa) care must be taken to ensure that incorrect data is not latched through to the output. In other words, if LDAC goes low while WR and either CS input are low (or WR and either CS go low while LDAC is low), then the LDAC signal must stay low for t7 or longer after WR returns high to ensure correct data is latched through to the output. The write cycle timing diagram for the AD7248A is shown in Figure 7. Figure 7. AD7248A Write Cycle Timing Diagram An alternate scheme for writing data to the AD7248A is to tie the CSMSB and LDAC inputs together. In this case exercising CSLSB and WR latches the lower 8 bits into the input latch. The second write, which exercises CSMSB, WR and LDAC loads the upper 4-bit nibble to the input latch and at the same time transfers the 12-bit data to the DAC latch. This automatic transfer mode updates the output of the AD7248A in two write operations. This scheme works equally well for CSLSB and LDAC tied together provided the upper 4-bit nibble is loaded to the input latch followed by a write to the lower 8 bits of the in- put latch. Table II. AD7248A Truth Table CSLSB CSMSB WR LDAC Function L H L H I.oad LS Byte into Input Latch LH g H Latches LS Byte into Input Latch g H L H Latches LS Byte into Input Latch H L L H Loads MS Nibble into Input Latch HL g H Latches MS Nibble into Input Latch H g L H Latches MS Nibble into Input Latch H H H L Loads Input Latch into DAC Latch HH H g Latches Input Latch into DAC Latch H L L L Loads MS Nibble into Input Latch and Loads Input Latch into DAC Latch H H H H No Data Transfer Operation H = High State L = Low State APPLYING THE AD7245A/AD7248A The internal scaling resistors provided on the AD7245A/ AD7248A allow several output voltage ranges. The part can produce unipolar output ranges of 0 V to +5 V or 0 V to +10 V and a bipolar output range of –5 V to +5 V. Connections for the various ranges are outlined below. UNIPOLAR (0 V TO +10 V) CONFIGURATION The first of the configurations provides an output voltage range of 0 V to +10 V. This is achieved by connecting the bipolar off- set resistor, ROFS, to AGND and connecting RFB to VOUT. In this configuration the AD7245A/AD7248A can be operated single supply (VSS = 0 V = AGND). If dual supply performance is required, a VSS of –12 V to –15 V should be applied. Figure 8 shows the connection diagram for unipolar operation while the table for output voltage versus the digital code in the DAC latch is shown in Table III. Figure 8. Unipolar (0 to +10 V) Configuration Table III. Unipolar Code Table (0 V to +10 V Range) DAC Latch Contents MSB LSB Analog Output, VOUT 1 1 1 1 1 1 1 1 1 1 1 1 +2 VREF 4095 4096 1 0 0 0 0 0 0 0 0 0 0 1 +2 VREF 2049 4096 1 0 0 0 0 0 0 0 0 0 0 0 +2 VREF 2048 4096 =+V REF 0 1 1 1 1 1 1 1 1 1 1 1 +2 VREF 2047 4096 0 0 0 0 0 0 0 0 0 0 0 1 +2 VREF 1 4096 0 0 0 0 0 0 0 0 0 0 0 0 0 V NOTE: 1 LSB = 2 VREF(2 –12) = V REF 1 2048 UNIPOLAR (0 V TO +5 V) CONFIGURATION The 0 V to +5 V output voltage range is achieved by tying ROFS, RFB and VOUT together. For this output range the AD7245A/ AD7248A can be operated single supply (VSS = 0 V) or dual supply. The table for output voltage versus digital code is as in Table III, with 2 • VREF replaced by VREF. Note that for this range 1 LSB = VREF(2 –12) = V REF 1 4096 . |
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Podobny opis - AD7248AAQ |
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