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AD8804AR Arkusz danych(PDF) 5 Page - Analog Devices |
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AD8804AR Arkusz danych(HTML) 5 Page - Analog Devices |
5 / 16 page AD8802/AD8804 REV. 0 –5– 100 0.0001 2.5 0.01 0.001 0.5 0 0.1 1.0 10 2 1.5 1 INPUT VOLTAGE – Volts 5 3 4.5 4 3.5 TA = +25°C ALL DIGITAL INPUTS TIED TOGETHER VDD = +5V VDD = +3V Figure 7. Supply Current vs. Logic Input Voltage 80 60 40 20 0 100 100k 10k 1k 10 FREQUENCY – Hz VDD = +5V ALL OUTPUTS SET TO MIDSCALE (80H) Figure 8. Power Supply Rejection vs. Frequency 10 0% 100 90 0% VDD = +5V VREF = +5V TIME – 5µs/DIV 4V 0V 5V 0V OUT CS 2V 5µs 6V 2V 5V Figure 9. Large-Signal Settling Time 10 0% 100 90 OUTPUT1: OOH → FFH TIME – 0.2µs/DIV 10mV 200ns VDD = +5V VREF = +5V f = 1MHz Figure 10. Adjacent Channel Clock Feedthrough 10 0% 100 90 OUTPUT1: 7FH → 80H VDD = +5V VREF = +5V TIME – 1µs/DIV OUT1 5mV/DIV CS 5V/DIV 5mV 1µs 5V Figure 11. Midscale Transition HOURS OF OPERATION AT 150 °C 0.01 –0.01 0 –0.005 0.005 0 600 100 300 500 VDD = +4.5V VREF = +4.5V SS = 176 PCS VREFL = 0V 200 400 Figure 12. Zero-Scale Error Accelerated by Burn-In |
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