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AD9002BJ Arkusz danych(PDF) 6 Page - Analog Devices

Numer części AD9002BJ
Szczegółowy opis  High Speed 8-Bit Monolithic A/D Converter
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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AD9002BJ Arkusz danych(HTML) 6 Page - Analog Devices

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AD9002
–6–
REV. D
LAYOUT SUGGESTIONS
Designs using the AD9002, like all high speed devices, must
follow a few basic layout rules to insure optimum performance.
Essentially, these guidelines are meant to avoid many of the
problems associated with high speed designs. The first require-
ment is for a substantial ground plane around and under the
AD9002. Separate ground plane areas for the digital and analog
components may be useful, but these separate grounds should
be connected together at the AD9002 to avoid the effects of
“ground loop” currents.
The second area that requires an extra degree of attention in-
volves the three reference inputs, +VREF, REFMID, and –VREF.
The +VREF input and the –VREF input should both be driven
from a low impedance source (note that the +VREF input is
typically tied to analog ground). A low drift amplifier should
provide satisfactory results, even over an extended temperature
range. Adjustments at the REFMID input may be useful in im-
proving the integral linearity by correcting any reference ladder
skews. The application circuit shown below demonstrates a
simple and effective means of driving the reference circuit.
The reference inputs should be adequately decoupled to ground
through 0.1
µF chip capacitors to limit the effects of system
noise on conversion accuracy. The power supply pins must also
be decoupled to ground to improve noise immunity; 0.1
µF and
0.01
µF chip capacitors are recommended.
The analog input signal is brought into the AD9002 through
two separate input pins. It is very important that the two input
pins be driven symmetrically with equal length electrical con-
nections. Otherwise, aperture delay errors may degrade con-
verter performance at high frequencies.
APPLICATION INFORMATION
The AD9002 is compatible with all standard ECL logic families,
including 10K and 10KH. 100K ECL’s logic levels are tempera-
ture compensated, and are therefore compatible with the
AD9002 (and most other ECL device families) only over a
limited temperature range. To operate at the highest encode
rates, the supporting logic around the AD9002 will need to be
equally fast. Whichever of the ECL logic families is used, special
care must be exercised to keep digital switching noise away from
the analog circuits around the AD9002. The two most critical
items are digital supply lines and digital ground return.
The input capacitance of the AD9002 is an exceptionally low
17 pF. This allows the use of a wide range of input amplifiers,
both hybrid and monolithic. To take full advantage of the wide
input bandwidth of the AD9002, a hybrid amplifier such as the
AD9610 will be required. For those applications that do not
require the full input bandwidth of the AD9002, more tradi-
tional monolithic amplifiers, such as the AD846, will work very
well. Overall performance with any amplifier can be improved
by inserting a 10
Ω resistor in series with the amplifier output.
The output data is buffered through the ECL compatible output
latches. All data is delayed by one clock cycle, in addition to the
latch propagation delay (tPD), before becoming available at the
outputs. Both the analog-to-digital conversion cycle and the
data transfer to the output latches are triggered on the rising
edge of the differential, ECL compactible ENCODE signal (see
timing diagram). In applications where only a single-ended
signal is available, the AD96685, a high speed, ECL voltage
comparator, can be employed to generate the differential sig-
nals. All ECL signals (including the overflow bit) should be
terminated properly to avoid ringing and reflection.
The AD9002 also incorporates a HYSTERESIS control pin
which provides from 0 mV to 10 mV of additional hysteresis in
the comparator input stages. Adjustments in the HYSTERESIS
control voltage may help improve noise immunity and overall
performance in harsh environments.
The OVERFLOW INHIBIT pin of the AD9002 determines
how the converter handles overrange inputs (AIN
≥ +V
REF). In
the “enabled” state (floating at –5.2 V), the OVERFLOW out-
put will be at logic HIGH and all other outputs will be at logic
LOW for overrange inputs (return-to-zero operation). In the
“inhibited” state (tied to ground), the OVERFLOW output will
be at logic LOW, and all other outputs will be at logic HIGH
for overrange inputs (nonreturn-to-zero operation).
The AD9002 provides outstanding error rate performance. This
is due to tight control of comparator offset matching and a fault
tolerant decoding stage. Additional improvements in error rate
are possible through the addition of hysteresis (see HYSTER-
ESIS control pin). This level of performance is extremely im-
portant in fault-sensitive applications such as digital radio
(QAM).
Dramatic improvements in comparator design and construction
give the AD9002 excellent dynamic characteristics, especially
SNR (signal-to-noise ratio). The 160 MHz input bandwidth
and low error rate performance give the AD9002 an SNR of
48 dB with a 1.23 MHz input. High SNR performance is par-
ticularly important in wide bandwidth applications, such as
pulse signature analysis, commonly performed in advanced
radar receivers.
100
2N3906
OVERFLOW
D8 (MSB)
D7
D6
D5
D4
D3
D2
D1 (LSB)
–5.2D
–5.2A
0.01 F
0.1 F
0.1 F
0.01 F
ENCODE
ENCODE
AIN
AIN
–VREF +VREF
0.1 F
10
0.1 F
AD741
AD9611
AD96685
40
AD9002
EQUAL
DISTANCE
50
ENCODE
INPUT
(GROUND
THRESHOLD)
ANALOG
INPUT
(0V TO +2V)
1k
4k
–15V
1.5k
50
NYQUEST
FILTER
Figure 5. Typical Application


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