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AD9040AJR Arkusz danych(PDF) 6 Page - Analog Devices |
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AD9040AJR Arkusz danych(HTML) 6 Page - Analog Devices |
6 / 12 page AD9040A REV. B –6– THEORY OF OPERATION Refer to the block diagram. The AD9040A employs subranging architecture and digital error correction. This combination of design techniques insures true 10-bit accuracy at the digital outputs of the converter. At the input, the analog signal is applied to a track-and-hold (T/H) that holds the analog value which is present when the unit is strobed with an ENCODE command. The conversion process begins on the rising edge of this pulse, which should have a 50% ( ±10%) duty cycle. Minimum encode rate of the AD9040A is 10 MSPS because of the use of three internal T/H devices. The held analog value of the first track-and-hold is applied to a 5-bit flash converter and a pair of internal T/Hs (shown in the block diagram as a single unit). The T/Hs pipeline the analog signal to the amplifier array through a residue ladder and switch- ing circuit while the 5-bit flash converter resolves the most significant bits (MSBs) of the held analog voltage. When the 5-bit flash converter has completed its cycle, its out- put activates 1-of-32 ladder switches; these, in turn, cause the correct residue signal to be applied to the error amplifier array. The output of the error amplifier is applied to a 6-bit flash con- verter whose output supplies the five least significant bits (LSBs) of the digital output along with one bit of error correction for the 5-bit main range converter. Decode logic aligns the data from the two converters and pre- sents the result as a 10-bit parallel digital word. The output stage of the AD9040A is CMOS. Output data are strobed on the trailing edge of the ENCODE command. Full-scale range of the AD9040A is determined by the reference voltage applied to the VRFF (Pin 6) input. This voltage sets the internal flash and residue ladder voltage drops; these establish the value of the LSB. Because of headroom restraints, the full- scale range cannot be increased by applying a higher-than specified reference voltage. Conversely, a lower reference volt- age will reduce the full-scale range of the converter, but will also decrease its performance. An internal bandgap reference voltage of +2.5 V is provided to assure optimum performance over the operating temperature range. USING THE AD9040A Timing The duty cycle of the encode clock for the AD9040A is critical for obtaining rated performance of the ADC. Internal pulse widths within the track-and-hold are established by the encode command pulse width; to ensure rated performance, the duty cycle should be held at 50%. Duty cycle variations of less than ±10% will cause no degradation in performance. Operation at encode rates less than 10 MSPS is not recom- mended. The internal track-and-hold saturates, causing errone- ous conversions. This T/H saturation precludes clocking the AD9040A in burst mode. The 50% duty cycle must be main- tained even for sample rates down to 10 MSPS. The AD9040A provides latched data outputs, with 2 1/2 pipe- line delays. Data outputs are available one propagation delay (tPD) after the falling edge of the encode command (refer to AD9040A Timing Diagram). The length of the output data lines and the loads placed on them should be minimized to reduce transients within the AD9040A; these transients can detract from the converter’s dynamic performance. Voltage Reference A stable voltage reference is required to establish the 2-V p-p range of the AD9040A. There are two options for creating this reference. The easiest and least expensive way to implement it is to use the (+2.5 V) bandgap voltage reference which is internal to the ADC. Figure 3 illustrates the connections for using the internal reference. The internal reference has 500 µA of extra drive current which can be used for other circuits. REF AMP BANDGAP REFERENCE REFERENCE +2.5V AD9040A 0.1 F VOUT VREF –VS BPREF Figure 3. Using Internal Reference Some applications may require greater accuracy, improved temperature performance, or adjustment of the gain (input range) of the AD9040A which cannot be obtained by using the internal reference. For these applications, an external +2.5 V reference can be used, as shown in Figure 4. The VREF input requires 5 µA of drive current. REF AMP BANDGAP REFERENCE REFERENCE AD9040A 0.1 F VOUT VREF –VS BPREF REFERENCE 0.1 F Figure 4. Using External Reference |
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