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AD9054BST-200 Arkusz danych(PDF) 11 Page - Analog Devices |
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AD9054BST-200 Arkusz danych(HTML) 11 Page - Analog Devices |
11 / 20 page AD9054 –11– REV. 0 APPLICATION NOTES THEORY OF OPERATION The AD9054 combines Analog Devices’ patented MagAmp bit- per-stage architecture with flash converter technology to create a high performance, low power ADC. For ease of use the part includes an onboard reference and input logic that accepts TTL, CMOS or PECL levels. The analog input signal is buffered by a high-speed differential amplifier and applied to a track-and-hold (T/H) circuit. This T/H captures the value of the input at the sampling instant and maintains it for the duration of the conversion. The sampling and conversion process is initiated by a rising edge on the ENCODE input. Once the signal is captured by the T/H, the four Most Significant Bits (MSBs) are sequentially encoded by the MagAmp string. The residue signal is then encoded by a flash comparator string to generate the four Least Significant Bits (LSBs). The comparator outputs are decoded and com- bined into the eight-bit result. If the user has selected Single Channel Mode ( DEMUX = HIGH), the eight-bit data word is directed to the Channel A output bank. Data are strobed to the output on the rising edge of the ENCODE input with four pipeline delays. If the user has selected Dual Channel Mode ( DEMUX = LOW) the data are alternately directed between the A and B output banks and have five pipeline delays. At power-up, the N sample data can ap- pear at either the A or B port. To align the data in a known state the user must strobe DATA SYNC (DS, DS) per the conditions described in the Timing section. Graphics Applications The high bandwidth and low power of the AD9054 make it very attractive for applications that require the digitization of presampled waveforms, wherein the input signal rapidly slews from one level to another and is relatively stable for a period of time. Examples of these include digitizing the output of com- puter graphic display systems and very high speed solid state imagers. These applications require the converter to process inputs with frequency components well in excess of the sampling rate (often with subnanosecond rise times), after which the A/D must settle and sample the input in well under one pixel time. The archi- tecture of the AD9054 is vastly superior to older flash architec- tures, which not only exhibit excessive input capacitance (which is very hard to drive) but can make major errors when fed a very rapidly slewing signal. The AD9054’s extremely wide bandwidth Track/Hold circuit processes these signals without difficulty. Using the AD9054 Good high speed design practices must be followed when using the AD9054. To obtain maximum benefit, decoupling capaci- tors should be physically as close to the chip as possible. We recommend placing a 0.1 µF capacitor at each power-ground pin pair (9 total) for high frequency decoupling, and including one 10 µF capacitor for local low frequency decoupling. The VREF IN pin should also be decoupled by a 0.1 µF capacitor. The part should be located on a solid ground plane and output trace lengths should be short (<1 inch) to minimize transmis- sion line effects. This avoids the need for termination resistors on the output bus and reduces the load capacitance that needs to be driven, which in turn minimizes on-chip noise due to heavy current flow in the outputs. We have obtained optimum performance on our evaluation board by tying all VDD pins to a quiet analog power supply system, and tying all GND pins to a quiet analog system ground. Minimum Encode Rate The minimum sampling rate for the AD9054 is 25 MHz. To achieve very high sampling rates, the track/hold circuit employs a very small hold capacitor. When operated below the minimum guaranteed sampling rate, the T/H droop becomes excessive. This is first observed as an increase in offset voltage, followed by degraded linearity at even lower frequencies. Lower effective sampling rates may be easily supported by oper- ating the converter in dual port output mode and using only one output channel. A majority of the power dissipated by the AD9054 is static (not related to conversion rate) so the penalty for clock- ing at twice the desired rate is not high. Reference The AD9054 internal reference, VREF, provides a simple, cost effective reference for many applications. It exhibits reasonable accuracy and excellent stability over power supply and tempera- ture variations. The VREF OUT pin can simply be strapped to the VREF IN pin. The internal reference can be used to drive additional loads (up to several mA), including multiple A/D con- verters as might be required in a triple video converter application. When an external reference is desired for accuracy or other requirements, the AD9054 should be driven directly by the external reference source connected to pin VREF IN (VREF OUT can be left floating). The external reference can be set to 2.5 V ± 0.25 V. If VREF IN is raised by 10% (set to 2.75 V) the analog full-scale range will increase by 10% to 1.024 × 1.1 = 1.1264 V. The new input range will then be AIN ±0.5632 V. Digital Inputs SNR performance is directly related to the sampling clock sta- bility in A/D converters, particularly for high input frequencies and wide bandwidths. A low jitter clock (<10 ps @ 100 MHz) is essential for optimum performance when digitizing signals that are not presampled. ENCODE and Data Select (DS) can be driven differentially or single-ended. For single-ended operation, the complement inputs ( ENCODE, DS) are internally biased to V DD/3 (~1.5 V) by a high impedance on-chip resistor divider (Figure 5), but they may be externally driven to establish an alternate threshold if desired. A 0.1 µF decoupling capacitor to ground is sufficient to maintain a threshold appropriate for TTL or CMOS logic. TAMB – C 2.502 2.501 2.498 –40 100 –20 0 20 40 60 80 2.500 2.499 Figure 33. Reference Voltage vs. Temperature |
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