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AD9059PCB Arkusz danych(PDF) 4 Page - Analog Devices |
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AD9059PCB Arkusz danych(HTML) 4 Page - Analog Devices |
4 / 12 page AD9059 –4– REV. 0 PIN DESCRIPTIONS Pin No. Name Function 1, 28 AINA, AINB Analog Inputs for ADC A and B. 2 VREF Internal Voltage Reference (+2.5 V Typical); Bypass with 0.1 µF to Ground or Overdrive with External Voltage Reference. 3 PWRDN Power-Down Function Select; Logic HIGH for Power-Down Mode (Digital Outputs Go to High- Impedance State). 4, 25 VD Analog +5 V Power Supply. 5, 24, 27 GND Ground. 6, 23 VDD Digital Output Power Supply. Nominally +3 V to +5 V. 7–14 D7A–D0A Digital Outputs of ADCA. 22–15 D7B–D0B Digital Outputs of ADCB. 26 ENCODE Encode Clock for ADCs A and B (ADCs Sample Simultaneously On the Rising Edge of ENCODE). Table I. Digital Coding (VREF = +2.5 V) Analog Input Voltage Level Digital Output 3.0 V Positive Full Scale 1111 1111 2.502 V Midscale + 1/2 LSB 1000 0000 2.498 V Midscale – 1/2 LSB 0111 1111 2.0 V Negative Full Scale 0000 0000 N N + 3 N + 5 N + 1 N + 2 N + 4 tA tV tPD tEH tEL N – 3 N – 2 N – 1 N N + 1 N + 2 ENCODE AIN DIGITAL OUTPUTS tA tEH tEL tV tPD APERTURE DELAY PULSE WIDTH HIGH PULSE WIDTH LOW OUTPUT VALID TIME OUTPUT PROP DELAY 6.7ns 6.7ns 4.0ns 2.7ns 6.6ns 9.5ns 166ns 166ns 14.2ns MIN TYP MAX Figure 1. Timing Diagram PIN CONFIGURATION 14 13 12 11 10 17 16 15 19 18 20 28 27 26 25 24 23 22 21 9 8 1 2 3 4 7 6 5 TOP VIEW (Not to Scale) AD9059 AINA VD ENCODE GND AINB VREF PWRDN VD D7B (MSB) VDD GND GND VDD D7A (MSB) D6A D5A D4A D4B D5B D6B D3A D2A D1A D0A (LSB) D3B D0B (LSB) D1B D2B |
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