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AD9066JR Arkusz danych(PDF) 2 Page - Analog Devices

Numer części AD9066JR
Szczegółowy opis  Dual 6-Bit, 60 MSPS Monolithic A/D Converter
Download  7 Pages
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD9066JR Arkusz danych(HTML) 2 Page - Analog Devices

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ELECTRICAL CHARACTERISTICS
Test
AD9066JR
AD9066AR/ARS
Parameter
Level
Temp
Min
Typ
Max
Min
Typ
Max
Unit
ANALOG INPUT
Full-Scale Input Range
VI
Full
475
500
525
450
500
530
mV
Gain Matching (FS Range)
IV
Full
16
16
mV
DC Input (Midscale)
1
V
+25
°C+VS – 1.1
+VS – 1.1
V
Input Offset
1
VI
Full
–1.0
+1.0
–1.0
+1.0
LSBs
Input Capacitance
IV
Full
10
15
10
15
pF
Input Resistance (DC)
VI
Full
25
45
55
22
45
57
k
Input Bandwidth (3 dB)
V
+25
°C
100
100
MHz
Gain Flatness (to 15 MHz)
V
+25
°C
0.25
0.25
dB
Integral Linearity
VI
Full
–1.0
+1.0
–1.0
+1.0
LSBs
Differential Linearity
VI
Full
–0.5
+0.5
–0.5
+0.5
LSBs
Monotonicity
VI
Full
Guaranteed
Guaranteed
SWITCHING PERFORMANCE
Max Conversion Rate
VI
Full
60
60
MSPS
Output Delay (tV)
2
IV
Full
4
4
ns
Output Delay (tPD)
2
IV
Full
11
12
ns
Aperture Uncertainty (Jitter)
V
+25
°C
10
10
ps rms
Aperture Time (tA)
V
+25
°C
1.0
1.0
ns
DYNAMIC PERFORMANCE
3
Effective Number of Bits
VI
+25
°C
5.3
5.7
5.2
5.7
Bits
SINAD
VI
+25
°C
3436
3336
dB
Harmonic Distortion (THD)
VI
+25
°C
4050
4050
dB
Crosstalk Rejection
IV
+25
°C
4050
4050
dBc
ENCODE INPUT
Logic High Voltage
VI
Full
2.0
2.0
V
Logic Low Voltage
VI
Full
0.8
0.8
V
Input High Current
VI
Full
500
500
µA
Input Low Current
VI
Full
500
500
µA
Pulsewidth High
IV
Full
7.0
7.0
ns
Pulsewidth Low
IV
Full
7.0
7.0
ns
DIGITAL OUTPUTS
Output Coding
Full
Offset Binary
Offset Binary
Logic High Voltage (IOH = 1 mA)
VI
Full
3.8
3.8
V
Logic Low Voltage (IOL = 1 mA)
VI
Full
0.4
0.4
V
POWER SUPPLY
+VS Supply Voltage
VI
Full
4.75
5.25
4.75
5.25
V
Power Supply Rejection Ratio
1
IV
Full
110
130
110
130
mV/V
+VS Supply Current
VI
Full
80
120
80
120
mA
Power Dissipation
4
VI
Full
400
600
400
600
mW
NOTES
1For ac coupled applications, the ADC is internally biased to insure that the midpoint transition of the ADC is within the limits specified with no signal applied. For
dc coupled applications, the dc value of the midpoint transition voltage will track the supply voltage within the limits shown for dc input (midscale) plus the dc offset.
Power Supply Rejection Ratio (PSRR) refers to the variation of the input signal range (gain) to supply voltage.
2t
V and tPD are measured from the 1.4 V level of the Clock and the 50% level between VOH and VOL. The ac load on all the digital outputs during test is 10 pF (max),
the dc load will not exceed
±40 µA.
3Effective number of bits (ENOB) and THD are measured using a FFT with a pure sine wave analog input @ 15.5 MHz, 1 dB below full scale. ENOB is calculated by
ENOB = (SNR – 1.76 dB)/6.02; THD is measured from full scale to the sum of the second through seventh harmonic of the input.
4Typical thermal impedance for the “R” style (SOIC) 28-lead package is:
θ
JC = 4
°C/W, θ
CA = 41
°C/W, θ
JA = 45
°C/W, and the “RS” style (SSOP) 28-lead package is:
θ
JC = 26.97
°C/W, θ
CA = 51.61
°C/W, θ
JA = 78.58
°C/W.
Specifications subject to change without notice.
AD9066–SPECIFICATIONS
REV. A
–2–
(+VS = +5 V, AIN = 15.5 MHz, Encode Rate = 60 MSPS, TC = TA)


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