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AD9071 Arkusz danych(PDF) 8 Page - Analog Devices |
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AD9071 Arkusz danych(HTML) 8 Page - Analog Devices |
8 / 12 page AD9071 –8– REV. B APPLICATION NOTES THEORY OF OPERATION The AD9071 employs a two-step subranging architecture with digital error correction. The sampling and conversion process is initiated by a rising edge at the ENCODE input. The analog input signal is buffered by a high speed differential amplifier and applied to a track-and-hold (T/H) circuit, which captures the value of the input at the sam- pling instant and maintains it for the duration of the conversion. The coarse quantizer (ADC) produces a 5-bit estimate of the input value. Its digital output is reconverted to analog form by the reconstruction DAC and subtracted from the input signal in the SUM AMP. The second stage quantizer generates a 6-bit representation of the difference signal. The eleven bits are pre- sented to the ENCODE LOGIC, which corrects for range over- lap errors and produces an accurate 10-bit result. Data are strobed to the output on the rising edge of the ENCODE input, with the data from sample N appearing on the output following ENCODE rising edge N+3. USING THE AD9071 ENCODE Input Any high-speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. A track/hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock will be combined with the desired signal at the A/D output. For that reason, considerable care has been taken in the design of the ENCODE input of the AD9071, and the user is advised to give commensurate thought to the clock source. The lowest jitter clock source is a crystal oscillator pro- ducing a pure sine wave. The ENCODE input is fully TTL/CMOS compatible. Digital Outputs The digital outputs are CMOS compatible for lower power consumption. 200 Ω series resistors are recommended between the AD9071 and the receiving logic to reduce transients and improve SNR. Analog Input The analog input has been optimized for differential signal input. AD9071 T1A T1 - 1T 50 VREF (+2.5V) 0.1 F 0.1 F 100 100 AIN AIN Figure 18. Differential Analog Input Configuration If driven single-endedly, the AIN should be connected to a clean reference and bypassed to ground. For best dynamic performance, impedances at AIN and AIN should match. Special care was taken in the design of the analog input section of the AD9071 to prevent damage and corruption of data when the input is overdriven. The nominal input range is +1.988 V to +3.012 V (1.024 V p-p centered at +2.5 V). Out-of-range comparators detect when the analog input signal is out of this range, and set the OR output signal HIGH. The digital outputs are locked at plus or minus full scale (3FFH or 200H) for volt- ages that are out of range, but between 1 V and 5 V. Input volt- ages outside of this range may result in invalid codes at the ADC’s output. 25 AD9071 50 VREF (+2.5V) 0.1 F 0.1 F 100 100 AIN AIN Figure 19. Single-Ended Analog Input Configuration When the analog input signal returns to the nominal range, the out-of-range comparators return the ADC to its active mode and the device recovers in the overvoltage recovery time. Voltage Reference A stable and accurate 2.5 V voltage reference (VCC – 2.5 V) is built into the AD9071 (VREF OUT). In normal operation, the internal reference is used by strapping Pins 3 and 4 of the AD9071 together. The internal reference can provide 100 µA of extra drive current that may be used for other circuits. Some applications may require greater accuracy, improved temperature performance, or adjustment of the gain of the AD9071, which cannot be obtained by using the internal refer- ence. For these applications, an external 2.5 V reference can be connected to VREF IN, which requires 5 µA of drive current (see Figure 20). AD9071 VREF IN 0.1 F AD780 VOUT +VIN GND 1 F +5V TRIM +5V 25k 1M O/P SELECT NC NC = NO CONNECT Figure 20. Using the AD780 Voltage Reference The input range can be adjusted by varying the reference volt- age applied to the AD9071. No appreciable degradation in performance occurs when the reference is adjusted ±4%. The full-scale range of the ADC tracks reference voltage changes linearly. Timing The performance of the AD9071 is insensitive to the duty cycle of the clock over a wide range of operating conditions (see Figure 15). The AD9071 provides latched data outputs, with three pipeline delays. Data outputs are available one propagation delay (tPD) after the rising edge of the encode command (see Figure 1). The length of the output data lines, and loads placed on them, should be minimized to reduce transients within the AD9071; these transients can detract from the converter’s dynamic performance. |
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