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AD9057-80 Arkusz danych(PDF) 8 Page - Analog Devices

Numer części AD9057-80
Szczegółowy opis  8-Bit 40 MSPS/60 MSPS/80 MSPS A/D Converter
Download  12 Pages
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD9057-80 Arkusz danych(HTML) 8 Page - Analog Devices

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AD9057
–8–
REV. B
The AD9057 provides high impedance digital output operation
when the ADC is driven into power-down mode (PWRDN,
logic HIGH). A 200 ns (minimum) power-down time should be
provided before a high impedance characteristic is required at
the outputs. A 200 ns power-up period should be provided to
ensure accurate ADC output data after reactivation (valid output
data is available three clock cycles after the 200 ns delay).
Timing
The AD9057 is guaranteed to operate with conversion rates
from 5 MSPS to 80 MSPS depending on grade. The ADC is
designed to operate with an encode duty cycle of 50%, but per-
formance is insensitive to moderate variations. Pulse width varia-
tions of up to
±10% (allowing the encode signal to meet the
minimum/maximum HIGH/LOW specifications) will cause no
degradation in ADC performance (see Figure 1 timing diagram).
Power Dissipation
The power dissipation of the AD9057 is specified to reflect a
typical application setup under the following conditions: analog
input is –0.5 dBFS at 10.3 MHz, VD is +5 V, VDD is +3 V, and
digital outputs are loaded with 7 pF typical (10 pF maximum).
The actual dissipation will vary as these conditions are modified
in user applications. Figure 8 shows typical power consumption
for the AD9057 versus ADC encode frequency and VDD supply
voltage.
A power-down function allows users to reduce power dissipation
when ADC data is not required. A TTL/CMOS HIGH signal
(PWRDN) shuts down portions of the ADC and brings total
power dissipation to less than 10 mW. The internal bandgap
voltage reference remains active during power-down mode to
minimize ADC reactivation time. If the power-down function is
not desired, Pin 1 should be tied to ground.
APPLICATIONS
The wide analog bandwidth of the AD9057 makes it attractive
for a variety of high performance receiver and encoder applica-
tions. Figure 16 shows two ADCs in a typical low cost I & Q
demodulator implementation for cable, satellite, or wireless
LAN modem receivers. The excellent dynamic performance of
the ADC at higher analog input frequencies and encode rates
empowers users to employ direct IF sampling techniques (refer
to Figure 3 spectral plot). IF sampling eliminates or simplifies
analog mixer and filter stages to reduce total system cost and
power.
BPF
BPF
AD9057
AD9057
VCO
90
°
VCO
IF IN
Figure 16. I & Q Digital Receiver
The high sampling rate and analog bandwidth of the AD9057
are ideal for computer RGB video digitizer applications. With a
full-power analog bandwidth of 2
× the maximum sampling
rate, the ADC provides sufficient pixel to pixel transient set-
tling time to ensure accurate 60 MSPS video digitization. Fig-
ure 17 shows a typical RGB video digitizer implementation for
the AD9057.
AD9057
AD9057
PLL
AD9057
PIXEL CLOCK
RED
GREEN
BLUE
H-SYNC
8
8
8
Figure 17. RGB Video Encoder
Evaluation Board
The AD9057/PCB evaluation board provides an easy to use
analog/digital interface for the 8-bit, 60 MSPS ADC. The
board includes typical hardware configurations for a variety of
high speed digitization evaluations. On board components
include the AD9057 (in the 20-pin SSOP package), an optional
analog input buffer amplifier, a digital output latch, board
timing drivers, an analog reconstruction digital-to-analog con-
verter, and configurable jumpers for ac coupling, dc coupling,
and power-down function testing. The board is configured at
shipment for dc coupling using the AD9057’s internal voltage
reference.
For dc coupled analog input applications, amplifier U2 is con-
figured to operate as a unity gain inverter with adjustable offset
for the analog input signal. For full-scale ADC drive the analog
input signal should be 1 V p-p into 50
Ω (R1) referenced to
ground (0 V). The amplifier offsets the analog signal by
+VREF (+2.5 V typical) to center the voltage for proper ADC
input drive. For dc coupled operation, connect E1 to E2 (ana-
log input to R2) and E11 to E12 (amplifier output to analog
input of AD9057) using the board jumper connectors. DC
offset of the analog input signal can be modified by adjusting
potentiometer R10.
For ac coupled analog input applications, amplifier U2 is
removed from the analog signal path. The analog signal is
coupled into the input of the AD9057 through capacitor C2.
The ADC pulls analog input bias current from the VREF IN
voltage through the 1 k
Ω resistor internal to the AD9057
(BIAS OUT). The analog input signal to the board should be
1 V p-p into 50
Ω (R1) for full-scale ADC drive. For ac
coupled operation, connect E1 to E3 (analog input A to C2
feedthrough capacitor) and E10 to E12 (C2 to the analog input
and internal bias resistor) using the board jumper connectors.
The onboard reference voltage may be used to drive the ADC
or an external reference may be applied. To use the internal
voltage reference, connect E6 to E5 (VREF OUT to VREF
IN). To apply an external voltage reference, connect E4 to E5
(external reference from the REF banana jack to VREF IN).
The external voltage reference should be +2.5 V
± 10%.


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