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AD9100SD Arkusz danych(PDF) 8 Page - Analog Devices |
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AD9100SD Arkusz danych(HTML) 8 Page - Analog Devices |
8 / 12 page AD9100 REV. B –8– Using Sockets Pin sockets (P/N 6-330808-3 from AMP) should be used if the device can not be soldered directly to the PCB. High profile or wire wrap type sockets will dramatically reduce the dynamic performance of the device in addition to increasing the case-to- ambient thermal resistance. Driving the Encode Clock The AD9100 requires a differential ECL clock command. Due to the high gain bandwidth of the AD9100 internal switch, the input clock should have a slew rate of at least 100 V/ µs. To obtain maximum signal to noise performance, especially at high analog input frequencies, a low jitter clock source is re- quired. The AD9100 clock can be driven by an AD96685, an ultrahigh speed ECL comparator with very low jitter. 150 150 1k 1k CLK CLK –5.2V –5.2V Figure 15. Clock/Clock Input Stage Driving the Analog Input Special care must be taken to ensure that the analog input signal is not compromised before it reaches the AD9100. To obtain maximum signal to noise performance, a very low phase noise analog source is required. In addition, input filtering and/or a low harmonic signal source is necessary to maximize the spuri- ous free dynamic range. Any required filtering should be done close to the AD9100 and away from any digital lines. Overdriving the Analog Input The AD9100 has input clamps that prevent hard saturation of the output buffer, thereby providing fast overvoltage recovery when the analog input transitions to the linear region ( ±2 V). The clamps are set internally at ±2.3 V and cannot be altered by the user. The output settles to 0.1% of its value 21 ns after the overvoltage condition is alleviated. When the analog input is outside the linear region, the analog output will be at either +2.2 V or –2.2 V. Matching the AD9100 to A/D Encoders The AD9100’s analog output level may have to be offset or amplified to match the full-scale range of a given A/D converter. This can generally be accomplished by inserting an amplifier after the AD9100. For example, the AD671 is a 12-bit 500 ns monolithic ADC encoder that requires a 0 to +5 V full-scale analog input. An AD84X series amplifier could be used to con- dition the AD9100 output to match the full-scale range of the AD671. Ultralow Distortion/Low Resistive Load Applications When driving low resistive loads or when the widest possible spurious free dynamic range is required, system performance can be improved by isolating the load from the AD9100. (See Figure 16.) The AD9620 low distortion closed-loop buffer amplifier has an input resistance of 800 k Ω and generates har- monics that are less than those generated by the AD9100. Other buffers should not be considered if their harmonics are not lower than those of the AD9100. AD9620 ANALOG INPUT INTO LOW RESISTIVE LOAD AD9100 Figure 16. Using AD9620 as Isolation Amplifier Direct IF Conversion The AD9100 can be used to sample super-Nyquist signals, making wide dynamic range direct IF to digital conversion prac- tical. By reducing the analog input level to the track and hold, distortion due to the AD9100 can be minimized. As the input level is reduced, the gain in the output amplifier (see Figure 17) must be increased to match the full scale level of the subsequent analog-to-digital converter. AD9100 POST-AMP ADC AD9618 T/H CLOCK ADC CLOCK IF INPUT 100 mV HOLD TRACK "1" "0" T/H CLOCK ADC CLOCK 20ns 5ns GAIN ADJ TO UTILIZE MAX ADC RANGE Figure 17. IF Sampling with Track-and-Hold This technique is not confined to processing Nyquist signals. Figure 18 illustrates the spurious free dynamic range of the AD9100 as a function of analog input signal level and frequency. Without the output amplifier (2 V p-p input), 70 dB+ dynamic range is observed only to about 24 MHz. By reducing the analog input to 200 mV p-p, >70 dB SFDR can be maintained to 70 MHz IFs. The optimum T/H input level for a particular IF can be deter- mined by examining the T/H spurious and noise performance. The highest input signal level which will provide the required SFDR gives the lowest noise performance. When sampling super Nyquist signals, the IF will be aliased to baseband and can be observed by using FFT analysis. 70 80 60 10 70 50 60 40 30 20 0 50 90 INPUT FREQUENCY – MHz 200mV p-p INPUT 500mV p-p INPUT 2V p-p INPUT Figure 18. SFDR vs. Input Frequency at 10 MSPS |
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Podobny opis - AD9100SD |
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