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AD9101AE Arkusz danych(PDF) 3 Page - Analog Devices |
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AD9101AE Arkusz danych(HTML) 3 Page - Analog Devices |
3 / 12 page NOTES 1If the analog input exceeds ±300 mV, the clock levels should be shifted as shown in the Theory of Operation section entitled “Driving the Encode Clock.” 2Time to recover within rated error band from 160% overdrive. 3Sampling bandwidth is defined as the –3 dB frequency response of the input sampler to the hold capacitor when operating in the sampling mode. It is greater than tracking bandwidth because it does not include the bandwidth of the output amplifier. 4Hold mode noise is proportional to the length of time a signal is held. For example, if the hold time (t H) is 20 ns, the accumulated noise is typically 3 µV (150 mV/s × 20 ns). This value must be combined with the track mode noise to obtain total noise. 5Total energy of worst case track-to-hold or hold-to-track glitch. Specifications subject to change without notice. –3– REV. 0 AD9101 20-Pin SOIC RTN RTN C B+ CLK NC V IN V OUT GND CLK GND GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 TOP VIEW (Not to Scale) AD9101 +V S +V S +V S +V S C B– –V S –V S –V S –V S 20-Contact Ceramic LCC 1 23 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 BOTTOM VIEW GND GND –VS NC VIN GND –VS +VS +VS +VS PIN CONFIGURATIONS ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage (+VS) . . . . . . . . . . . . . . . . . . . . –0.5 V to +6 V Supply Voltage (–VS) . . . . . . . . . . . . . . . . . . . . –6 V to +0.5 V Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 V CLOCK/CLOCK Input . . . . . . . . . . . . . . . . . –5 V to +0.5 V Continuous Output Current4 . . . . . . . . . . . . . . . . . . . . 70 mA Storage Temperature . . . . . . . . . . . . . . . . . . –65 °C to +150°C Operating Temperature Range AE, AR . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 °C to +85°C SE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55 °C to +125°C Junction Temperature (Ceramic) 2 . . . . . . . . . . . . . . . +175 °C Junction Temperature (Plastic)2 . . . . . . . . . . . . . . . . +150 °C Soldering Temperature (1 minute) 3 . . . . . . . . . . . . . . +220 °C NOTES 1Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2Typical thermal impedances (no air flow, soldered to PC board) are as follows: Ceramic LCC: θ JA = 48°C/W; θJC = 9.9°C/W; Plastic SOIC: θJA = 54°C/W; θ JC = 7.3°C/W. 3For surface mount devices, mounted by vapor phase soldering. Prior to vapor phase soldering, plastic units should receive a minimum eight hour bakeout at 110 °C to drive off any moisture absorbed in plastic during shipping or storage. Through-hole devices can be soldered at +300 °C for 10 seconds. 4Output is short circuit protected to ground. Continuous short circuit may affect device reliability. Pin Description Pin Description Connection 1 RTN Gain Set Resistor Return* 2 RTN Gain Set Resistor Return* 3CB+ Bootstrap Capacitor (Positive Bias) 4+VS +5 V Power Supply (Analog) 5+VS +5 V Power Supply (Analog) 6 GND Hold Capacitor Ground 7 GND Hold Capacitor Ground 8+VS +5 V Power Supply (Digital) 9+VS +5 V Power Supply (Digital) 10 CLK True ECL T/H Clock 11 CLK Complement ECL T/H Clock 12 –VS –5.2 V Power Supply (Digital) 13 –VS –5.2 V Power Supply (Digital) 14 N/C No Connection 15 VIN Analog Signal Input 16 GND Ground (Signal Return) 17 –VS –5.2 V Power Supply (Analog) 18 –VS –5.2 V Power Supply (Analog) 19 CB– Bootstrap Capacitor (Negative Bias) 20 VOUT Analog Signal Output *See “Matching the AD9101 to A/D Encoders.” Both pins should either be grounded or connected to voltage source for offset. WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9101 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. EXPLANATION OF TEST LEVELS Test Level I – 100% production tested. II – 100% production tested at +25 °C, and sample tested at specified temperatures. III – Periodically sample tested. IV – Parameter is guaranteed by design and characterization testing. V – Parameter is a typical value only. VI – All devices are 100% production tested at +25 °C. 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature extremes for commercial/industrial devices. ORDERING INFORMATION Temperature Package Package Model Range Description Option AD9101AR –40 °C to +85°C Plastic SOIC R-20 AD9101AE –40 °C to +85°C LCC E-20A AD9101SE –55 °C to +125°C LCC E-20A |
Podobny numer części - AD9101AE |
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Podobny opis - AD9101AE |
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