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AD9887KS-140 Arkusz danych(PDF) 1 Page - Analog Devices |
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AD9887KS-140 Arkusz danych(HTML) 1 Page - Analog Devices |
1 / 40 page REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD9887 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 Dual Interface for Flat Panel Displays FEATURES Analog Interface 140 MSPS Maximum Conversion Rate 330 MHz Analog Bandwidth 0.5 V to 1.0 V Analog Input Range 500 ps p-p PLL Clock Jitter at 140 MSPS 3.3 V Power Supply Full Sync Processing Midscale Clamp 4:2:2 Output Format Mode Digital (DVI 1.0 Compatible) Interface 112 MHz Operation (1 Pixel/Clock Mode) High Skew Tolerance of One Full Input Clock Sync Detect for “Hot Plugging” APPLICATIONS RGB Graphics Processing LCD Monitors and Projectors Plasma Display Panels Scan Converters Micro Displays Digital TV GENERAL DESCRIPTION The AD9887 offers designers the flexibility of a dual analog and digital interface for flat panel displays (FPDs) on a single chip. Both interfaces are optimized for excellent image quality supporting display resolutions up to SXGA (1280 × 1024 at 75 Hz). Either the analog or the digital interface can be selected by the user. Analog Interface For ease of design and to minimize cost, the AD9887 is a fully integrated interface solution for FPDs. The AD9887 includes an analog interface with a 140 MHz triple ADC with internal 1.25 V reference, PLL to generate a pixel clock from HSYNC, program- mable gain, offset, and clamp control. The user provides only a 3.3 V power supply, analog input, and HSYNC. Three-state CMOS outputs may be powered from 2.5 V to 3.3 V. The AD9887’s on-chip PLL generates a pixel clock from HSYNC. Pixel clock output frequencies range from 12 MHz to 140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS. When a COAST signal is presented, the PLL maintains its output fre- quency in the absence of HSYNC. A sampling phase adjustment is provided. Data, HSYNC and Clock output phase relationships are maintained. The PLL can be disabled and an external clock input provided as the pixel clock. The AD9887 also offers full sync pro- cessing for composite sync and sync-on-green applications. A clamp signal is generated internally or may be provided by the user through the CLAMP input pin. The analog interface is fully programmable via a 2-wire serial interface. FUNCTIONAL BLOCK DIAGRAM SERIAL REGISTER AND POWER MANAGEMENT SCL SDA A1 A0 2 DATACK HSOUT VSOUT SOGOUT Rx0+ Rx0– Rx1+ Rx1– Rx2+ Rx2– RxC+ RxC– RTERM DVI RECEIVER 8 8 8 ROUTA ROUTB 8 8 8 GOUTA GOUTB 8 8 8 BOUTA BOUTB 2 DATACK DE HSYNC VSYNC AD9887 DIGITAL INTERFACE ROUTA ROUTB GOUTA GOUTB BOUTA BOUTB HSOUT VSOUT SOGOUT DE DATACK 8 8 8 8 8 8 2 SYNC PROCESSING AND CLOCK GENERATION HSYNC COAST CLAMP CKINV CKEXT FILT CLAMP RAIN CLAMP GAIN CLAMP BAIN A/D 8 8 8 ROUTA ROUTB A/D 8 8 8 GOUTA GOUTB A/D 8 8 8 BOUTA BOUTB ANALOG INTERFACE M U X E S VSYNC SCDT REFIN REF REFOUT Digital Interface The AD9887 contains a Digital Video Interface (DVI 1.0) compat- ible receiver. This receiver supports displays ranging from VGA to SXGA (25 MHz to 112 MHz). The receiver operates with true color (24-bit) panels in 1 or 2 pixel(s)/clock mode, and also features an intrapair skew tolerance up to one full clock cycle. Fabricated in an advanced CMOS process, the AD9887 is pro- vided in a 160-lead MQFP surface mount plastic package and is specified over the 0 °C to 70°C temperature range. |
Podobny numer części - AD9887KS-140 |
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Podobny opis - AD9887KS-140 |
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