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ADMC401-PB Arkusz danych(PDF) 7 Page - Analog Devices

Numer części ADMC401-PB
Szczegółowy opis  Single-Chip, DSP-Based High Performance Motor Controller
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ADMC401-PB Arkusz danych(HTML) 7 Page - Analog Devices

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ADMC401
–7–
REV. B
Parameter
Min
Max
Unit
Bus Request/Grant
Timing Requirements:
t
BH
BR Hold after CLKOUT High1
0.25t
CK +2
ns
t
BS
BR Setup before CLKOUT Low1
0.25t
CK + 17
ns
Switching Characteristics:
t
SD
CLKOUT High to
DMS, PMS, BMS,
0.25t
CK + 10
ns
RD, WR Disable
t
SDB
DMS, PMS, BMS, RD, WR
Disable to
BG Low
0
ns
t
SE
BG High to DMS, PMS, BMS,
RD, WR Enable
0
ns
t
SEC
DMS, PMS, BMS, RD, WR
Enable to CLKOUT High
0.25t
CK – 7
ns
t
SDBH
DMS, PMS, BMS, RD, WR
Disable to
BGH Low2
0ns
t
SEH
BGH High to DMS, PMS, BMS,
RD, WR Enable2
0ns
NOTES
1
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized
on the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition for
BR/BG cycle relationships.
2
BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
BR
CLKOUT
PMS, DMS
BMS, RD
WR
BG
CLKOUT
BGH
tBH
tBS
tSD
tSDB
tSDBH
tSEH
tSE
tSEC
Figure 3. Bus Request–Bus Grant


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