FW322 datasheet(9/148 Pages) AGERE

Numer części	FW322

Szczegółowy opis	1394A PCI PHY/Link Open Host Controller Interface

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Producent	AGERE [Agere Systems]

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Lucent Technologies Inc.

9

Data Sheet, Rev. 1

FW322

February 2001

1394A PCI PHY/Link Open Host Controller Interface

FW322 Functional Description (continued)

sends the asynchronous interrupt status to the OHCI

interrupt handler block.

Asynchronous Transmit (ASYNC_TX)

The ASYNC_TX block of the FW322 manages the

asynchronous transmission of either request or

response packets. The mechanism for asynchronous

transmission of requests and responses are similar.

The only difference is the system memory location of

the buffer descriptor list when processing the two con-

texts. Therefore, the discussion below, which is for

asynchronous transmit requests, parallels that of the

asynchronous transmit response. The FW322 asyn-

chronous transmission of packets involves the following

steps:

1. Fetch complete buffer descriptor block from host

memory.

2. Get data from system memory and store into

async FIFO.

3. Request transfer of data from FIFO to link device.

4. Handle retries, if any.

5. Handle errors in steps 1 to 4.

6. End the transfer if there are no errors.

Asynchronous Receive (ASYNC_RX)

The ASYNC_RX block of the FW322 manages the

processing of received packets. Data packets are

parsed and stored in a dedicated asynchronous receive

FIFO. Command descriptors are read through the PCI

interface to determine the disposition of the data

arriving through the 1394 link.

The header of the received packet is processed to

determine, among other things, the following:

1. The type of packet received.

2. The source and destinations.

3. The data and size, if any.

4. The operation required, if any. For example, compare

and swap operation.

The ASYNC block also handles DMA transfers of self-

ID packets during the 1394 bus initialization phase and

block transactions associated with physical request.

Link Core

It is the responsibility of the link to ascertain if a

received packet is to be forwarded to the OHCI for

processing. If so, the packet is directed to a proper

inbound FIFO for either the isochronous block or the

asynchronous block to process. The link is also

responsible for CRC generation on outgoing packets

and CRC checking on receiving packets.

To become aware of data to be sent outbound on

1394 bus, the link must monitor the OHCI FIFOs look-

ing for packets in need of transmission. Based on data

received from the OHCI block, the link will form packet

headers for the 1394 bus. The link will alert the PHY

core as to the availability of the outbound data. It is the

link’s function to generate CRC for the outbound data.

The link also provides PHY core register access for the

OHCI.

PHY Core

The PHY core provides the analog physical layer func-

tions needed to implement a two-port node in a cable-

based IEEE 1394-1995 and IEEE 1394a-2000 network.

Each cable port incorporates two differential line trans-

ceivers. The transceivers include circuitry to monitor the

line conditions as needed for determining connection

status, for initialization and arbitration, and for packet

reception and transmission. The PHY core interfaces

with the link core.

The PHY core requires either an external 24.576 MHz

crystal or crystal oscillator. The internal oscillator drives

an internal phase-locked loop (PLL), which generates

the required 400 MHz reference signal. The 400 MHz

reference signal is internally divided to provide the

49.152 MHz, 98.304 MHz, and 196.608 MHz clock sig-

nals that control transmission of the outbound encoded

strobe and data information. The 49.152 MHz clock sig-

nal is also supplied to the associated LLC for

synchronization of the two chips and is used for resyn-

chronization of the received data.

The PHY/link interface is a direct connection and does

not provide isolation.

Data bits to be transmitted through the cable ports are

received from the LLC on two, four, or eight data lines

(D[0:7]), and are latched internally in the PHY in syn-

chronization with the 49.152 MHz system clock. These

bits are combined serially, encoded, and transmitted at

98.304 Mbits/s, 196.608 Mbits/s, or 393.216 Mbits/s as

the outbound data-strobe information stream. During

transmission, the encoded data information is transmit-

ted differentially on the TPA and TPB cable pair(s).

During packet reception, the TPA and TPB transmitters

of the receiving cable port are disabled, and the receiv-

ers for that port are enabled. The encoded data

information is received on the TPA and TPB cable pair.

The received data-strobe information is decoded to

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