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74F182SJ Arkusz danych(PDF) 2 Page - Fairchild Semiconductor |
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74F182SJ Arkusz danych(HTML) 2 Page - Fairchild Semiconductor |
2 / 8 page www.fairchildsemi.com 2 Unit Loading/Fan Out Functional Description The 74F182 carry lookahead generator accepts up to four pairs of Active LOW Carry Propagate (P0–P3) and Carry Generate (G0–G3) signals and an Active HIGH Carry input (Cn) and provides anticipated Active HIGH carries (Cn + x, Cn+y, Cn+z) across four groups of binary adders. The 74F182 also has Active LOW Carry Propagate (P) and Carry Generate (G) outputs which may be used for further levels of lookahead. The logic equations provided at the outputs are: Cn+x = G0 + P0 Cn Cn+y = G1 + P1 G0 + P1 P0 Cn Cn+z = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 Cn G = G 3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 P = P 2 P2 P1 P0 Also, the 74F182 can be used with binary ALUs in an active LOW or active HIGH input operand mode. The con- nections (Figure 1) to and from the ALU to the carry looka- head generator are identical in both cases. Carries are rippled between lookahead blocks. The critical speed path follows the circled numbers. There are several possible arrangements for the carry interconnects, but all achieve about the same speed. A 28-bit ALU is formed by dropping the last 74F181 or 74F381. *ALUs may be either 74F181 or 74F381 FIGURE 1. 32-Bit ALU with Rippled Carry between 16-Bit Lookahead ALUs Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL Cn Carry Input 1.0/2.0 20 µA/−1.2 mA G0, G2 Carry Generate Inputs (Active LOW) 1.0/14.0 20 µA/−8.4 mA G1 Carry Generate Input (Active LOW) 1.0/16.0 20 µA/−9.6 mA G3 Carry Generate Input (Active LOW) 1.0/8.0 20 µA/−4.8 mA P0, P1 Carry Propagate Inputs (Active LOW) 1.0/8.0 20 µA/−4.8 mA P2 Carry Propagate Input (Active LOW) 1.0/6.0 20 µA/−3.6 mA P3 Carry Propagate Input (Active LOW) 1.0/4.0 20 µA/−2.4 mA Cn+x − Cn+z Carry Outputs 50/33.3 −1 mA/20 mA G Carry Generate Output (Active LOW) 50/33.3 −1 mA/20 mA P Carry Propagate Output (Active LOW) 50/33.3 −1 mA/20 mA |
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