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74LCX841WM Arkusz danych(PDF) 2 Page - Fairchild Semiconductor |
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74LCX841WM Arkusz danych(HTML) 2 Page - Fairchild Semiconductor |
2 / 8 page www.fairchildsemi.com 2 Pin Descriptions Truth Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impendance NC = No Change Functional Description The LCX841 consists of ten D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchronous operation, as the output transition follows the data in transi- tion. On the LE HIGH-to-LOW transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description D0–D9 Data Inputs LE Latch Enable Input OE Output Enable Input O0–O9 3-STATE Latch Outputs Inputs Internal Output Function OE LE D Q O X X X X Z High Z H H L L Z High Z HHH H Z High Z H L X NC Z Latched L H L L L Transparent L H H H H Transparent L L X NC NC Latched |
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