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TS19460CSRLG Arkusz danych(PDF) 2 Page - Taiwan Semiconductor Company, Ltd |
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TS19460CSRLG Arkusz danych(HTML) 2 Page - Taiwan Semiconductor Company, Ltd |
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2 / 7 page  TS19460 AC/DC WLED Driver with External MOSFET Universal High Brightness 2/7 Version: A12 Electrical Specifications (TA= 25 oC, V IN= 12V, VLD=PWM=VDD, unless otherwise noted) Function Parameter Symbol Test Conditions Min Typ Max Units Input DC Input Voltage Range VINDC DC input voltage 8.0 -- 450 V Shut-down Mode Supply Current IINSD Pin PWMD to GND -- 0.5 1.0 mA Internal Regulator Internally Regulated Voltage VDD VIN=8V, IDD(EXT)=0 500pF at Gate, RT=226kΩ 7.25 7.5 7.75 V Line Regulation of VDD ∆VDDLine VIN=8~450V, IDD(EXT)=0 500pF at Gate, RT=226kΩ 0 -- 1.0 V Load Regulation of VDD ∆VDDLoad IDD(EXT)= 0 ~ 1mA 500pF at Gate, RT=226kΩ 0 -- 100 mV Undervoltage Lockout Threshold UVLO VDD rising 6.45 6.7 6.95 V Undervoltage Lockout Hysteresis ∆UVLO VDD falling -- 500 -- mV Maximum Input Current IIN (MAX) VIN=8V 3.5 -- -- mA Dimming PWMD Input Low Voltage VENL VIN=8V~450V -- -- 0.8 V PWMD Input High Voltage VENH VIN=8V~450V 2.0 -- -- V PWMD Pull-down resistance at PWMD REN VPWMD=5V 50 100 150 kΩ Average Current Sense Logic Current Sense Reference Voltage VCS 238 250 262 mV LD to Current Sense Ratio Av(LD) TA < +125ºC -- 0.18 -- LD input Voltage Shutdown VLD(OFF) VLD falling -- 150 -- mV LD input Voltage Enable ∆VLD(OFF) VLD rising -- 200 -- mV Current Sense Blanking Interval TBLANK 150 -- 280 nS Minimum On-Time TON(min) VCS= VCS + 30mV -- -- 1 uS Off Time TOFF RT=1MΩ 32 -- 48 uS RT=226kΩ 8 -- 12 Max. Steady-State Duty Cycle DMAX 75 -- -- % Short Circuit Protection Hiccup Threshold Voltage VCS 410 -- 470 mV Current Limit Delay CS to Gate TDELAY VCS= VCS + 30mV -- -- 150 nS Short Circuit Hiccup Time THICCUP 330 -- 460 uS Minimum On-Time (Short Circuit) TON(min) VCS= VDD -- -- 430 nS Gate Driver Gate Sourcing Current ISOURCE VGATE=0V, VDD=7.5V 165 -- -- mA Gate Sinking Current ISINK VGATE=VDD, VDD=7.5V 165 -- -- mA Gate output Rise Time TRISE CGATE=500pF, VDD=7.5V -- 30 50 nS Gate Output Fall Time TFALL CGATE=500pF, VDD=7.5V -- 30 50 nS Note 1: Limited by package power dissipation, whichever is lower |
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