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DM74AS169A Arkusz danych(PDF) 4 Page - Fairchild Semiconductor |
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DM74AS169A Arkusz danych(HTML) 4 Page - Fairchild Semiconductor |
4 / 6 page www.fairchildsemi.com 4 Switching Characteristics over recommended operating free air temperature range Note 3: Propagation delay time from up/down to ripple carry must be measured with the counter at either a minimum or a maximum count. As the logic level of the up/down input is changed, the ripple carry output will follow. If the count is minimum (0), the ripple carry output transition will be in phase. If the count is maximum, the ripple carry output will be out of phase. Symbol Parameter Conditions From To Min Max Units fMAX Maximum Clock Frequency VCC = 4.5V to 5.5V 75 MHz tPLH Propagation Delay Time RL = 500Ω Clock RIPPLE Carry 3 16.5 ns LOW-to-HIGH Level Output CL = 50 pF tPHL Propagation Delay Time Clock RIPPLE Carry 2 13 ns HIGH-to-LOW Level Output tPLH Propagation Delay Time Clock Any Q 1 7 ns LOW-to-HIGH Level Output tPHL Propagation Delay Time Clock Any Q 2 13 ns HIGH-to-LOW Level Output tPLH Propagation Delay Time En T RIPPLE Carry 1.5 9 ns LOW-to-HIGH Level Output tPHL Propagation Delay Time En T RIPPLE Carry 1.5 9 ns HIGH-to-LOW Level Output tPLH Propagation Delay Time U/D RIPPLE Carry 2 12 ns LOW-to-HIGH Level Output (Note 3) tPHL Propagation Delay Time U/D RIPPLE Carry 2 13 ns HIGH-to-LOW Level Output (Note 3) |
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