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DM74AS646WM Arkusz danych(PDF) 6 Page - Fairchild Semiconductor |
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DM74AS646WM Arkusz danych(HTML) 6 Page - Fairchild Semiconductor |
6 / 8 page www.fairchildsemi.com 6 DM74AS648 Switching Characteristics Note 7: These parameters are measured with the internal output state of the storage register opposite to that of the bus input. Symbol Parameter Conditions From To Min Max Units (Input) (Output) fMAX Maximum Clock Frequency VCC = 4.5V to 5.5V, 90 MHz tPLH Propagation Delay Time R1 = R2 = 500Ω 28.5 ns LOW-to-HIGH Level Output CL = 50 pF CAB or CBA A or B tPHL Propagation Delay Time 29 ns HIGH-to-LOW Level Output tPLH Propagation Delay Time 28 ns LOW-to-HIGH Level Output A or B B or A tPHL Propagation Delay Time 17 ns HIGH-to-LOW Level Output tPLH Propagation Delay Time 211 ns LOW-to-HIGH Level Output SBA or SAB A or B tPHL Propagation Delay Time 29 ns HIGH-to-LOW Level Output (Note 7) tPZH Output Enable Time 29 ns to HIGH Level Output tPZL Output Enable Time 315 ns to LOW Level Output Enable G A or B tPHZ Output Disable Time 29 ns from HIGH Level Output tPLZ Output Disable Time 29 ns from LOW Level Output tPZH Output Enable Time 316 ns to HIGH Level Output tPZL Output Enable Time 318 ns to LOW Level Output DIR A or B tPHZ Output Disable Time 210 ns from HIGH Level Output tPLZ Output Disable Time 210 ns from LOW Level Output |
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