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AD5551BRZ Arkusz danych(PDF) 6 Page - Analog Devices |
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AD5551BRZ Arkusz danych(HTML) 6 Page - Analog Devices |
6 / 16 page AD5551/AD5552 Rev. A | Page 6 of 16 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VOUT 1 AGND 2 VREF 3 CS 4 VDD 8 DGND 7 DIN 6 SCLK 5 AD5551 TOP VIEW (Not to Scale) Figure 4. AD5551 Pin Configuration RFB 1 VOUT 2 AGNDF 3 AGNDS 4 VDD 14 INV 13 DGND 12 LDAC 11 VREFS 5 DIN 10 VREFF 6 NC 9 CS 7 SCLK 8 AD5552 TOP VIEW (Not to Scale) NC = NO CONNECNT Figure 5. AD5552 Pin Configuration Table 4. AD5551 Pin Function Descriptions Pin No. Mnemonic Description 1 VOUT Analog Output Voltage from the DAC. 2 AGND Ground Reference Point for Analog Circuitry. 3 VREF This is the voltage reference input for the DAC. Connect to external reference ranges from 2 V to VDD. 4 CS This is an active low-logic input signal. The chip select signal is used to frame the serial data input. 5 SCLK Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. 6 DIN Serial Data Input. This device accepts 14-bit words. Data is clocked into the input register on the rising edge of SCLK. 7 DGND Digital Ground. Ground reference for digital circuitry. 8 VDD Analog Supply Voltage, 2.7 V to 5.5 V ± 10%. Table 5. AD5552 Pin Function Descriptions Pin No. Mnemonic Description 1 RFB Feedback Resistor. In bipolar mode, connect this pin to external op amp output. 2 VOUT Analog Output Voltage from the DAC. 3 AGNDF Ground Reference Point for Analog Circuitry (Force). 4 AGNDS Ground Reference Point for Analog Circuitry (Sense). 5 VREFS This is the voltage reference input (sense) for the DAC. Connect to external reference ranges from 2 V to VDD. 6 VREFF This is the voltage reference input (force) for the DAC. Connect to external reference ranges from 2 V to VDD. 7 CS This is an active low-logic input signal. The chip select signal is used to frame the serial data input. 8 SCLK Clock input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. 9 NC No Connect. 10 DIN Serial Data Input. This device accepts 14-bit words. Data is clocked into the input register on the rising edge of SCLK. 11 LDAC LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the input register. 12 DGND Digital Ground. Ground reference for digital circuitry. 13 INV Connected to the internal scaling resistors of the DAC. Connect the INV pin to external op amps inverting input in bipolar mode. 14 VDD Analog Supply Voltage, 2.7 V to 5.5 V ± 10%. |
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